Application-based dynamic heterogeneous many-core systems and methods

Abstract

A method for dynamically configuring multiple processors based on needs of applications includes receiving, from an application, an acceleration request message including a task to be accelerated. The method further includes determining a type of the task and searching a database of available accelerators to dynamically select a first accelerator based on the type of the task. The method further includes sending the acceleration request message to a first acceleration interface located at a configurable processing circuit. The first acceleration interface sends the acceleration request message to a first accelerator, and the first accelerator accelerates the task upon receipt of the acceleration request message.

1 . (canceled) 
     
     
         2 . A device, comprising:
 a first dynamic region of programmable logic circuitry configurable to comprise one or more accelerators;   a second dynamic region of the programmable logic circuitry configurable to comprise one or more accelerators; and   a static region comprising circuitry to support the first dynamic region and the second dynamic region, wherein the static region comprises programmable logic circuitry and is not to be reconfigured during a configuration of the first dynamic region or the second dynamic region.   
     
     
         3 . The device of  claim 2 , wherein the first dynamic region, the second dynamic region, the static region, or any combination thereof, comprise field programmable gate array (FPGA) programmable logic. 
     
     
         4 . The device of  claim 2 , wherein the first dynamic region is dynamically configurable to include a first set of the one or more accelerators based on a first application to be accelerated, and wherein the second dynamic region is dynamically configurable to include a second set of the one or more accelerators based on a second application to be accelerated. 
     
     
         5 . The device of  claim 4 , wherein dynamically configuring comprises adding, removing, or a combination thereof, at least one accelerator to the first set of the one or more accelerators and the second set of the one or more accelerators based at least in part on accelerators used to accelerate the first application or the second application. 
     
     
         6 . The device of  claim 2 , wherein the first dynamic region and the second dynamic region are to be partially reconfigured while the static region is not partially reconfigured. 
     
     
         7 . The device of  claim 2 , wherein the static region is configurable to communicate data over a peripheral component interconnect express (PCIe) interface. 
     
     
         8 . The device of  claim 2 , wherein at least one accelerator of the one or more accelerators is configurable to accelerate a task associated with media processing. 
     
     
         9 . The device of  claim 2 , wherein at least one accelerator of the one or more accelerators is configurable to accelerate a task associated with a real-time application. 
     
     
         10 . The device of  claim 2 , wherein at least one accelerator of the one or more accelerators is configurable to accelerate a task associated with media encoding. 
     
     
         11 . A system, comprising:
 a plurality of regions configurable to comprise one or more accelerators from a database of accelerators to accelerate a task; and   a static region not to be reconfigured, the static region comprising circuitry to support the plurality of regions.   
     
     
         12 . The system of  claim 11 , wherein the static region is configurable to communicate data over a peripheral component interconnect express (PCIe) interface. 
     
     
         13 . The system of  claim 11 , comprising: a network interface configurable to enable communication with the one or more accelerators of the database of accelerators over a network. 
     
     
         14 . The system of  claim 11 , wherein at least one accelerator of the one or more accelerators is to accelerate a task associated with media processing. 
     
     
         15 . The system of  claim 11 , wherein at least one accelerator of the one or more accelerators is to accelerate a task associated with encryption. 
     
     
         16 . The system of  claim 11 , wherein at least one of the plurality regions is reconfigurable to add, remove, or a combination thereof, an accelerator to accelerate a different task. 
     
     
         17 . A device, comprising:
 a first dynamic region configurable to comprise one or more accelerators of a database of accelerators; and   a second dynamic region configurable to comprise one or more accelerators of the database of accelerators, wherein the first dynamic region and the second dynamic region are hardware configurable.   
     
     
         18 . The device of  claim 17 , wherein a field programmable gate array (FPGA) comprises the first dynamic region and the second dynamic region. 
     
     
         19 . The device of  claim 17 , comprising: a static region configurable to support the first dynamic region and the second dynamic region, wherein the static region comprises programmable logic circuitry and is not to be reconfigured during a configuration of the first dynamic region or the second dynamic region. 
     
     
         20 . The device of  claim 19 , wherein the first dynamic region and the second dynamic region are to be partially reconfigured while the static region is not partially reconfigured. 
     
     
         21 . The device of  claim 19 , wherein the first dynamic region and the second dynamic region are to be partially reconfigured by adding, removing, or a combination thereof, at least one accelerator.