Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same

Abstract

Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

What is claimed is: 
     
         1 . A method of fabricating an integrated structure, the method comprising:
 forming a first fin comprising a silicon material, the first fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;   forming a second fin comprising the silicon material, the second fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;   forming a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly on sidewalls of the lower fin portion of the first fin and directly on sidewalls of the lower fin portion of the second fin, the layer comprising the PSG having a first end portion substantially co-planar with the shoulder feature of the first fin, and the layer comprising the PSG having a second end portion substantially co-planar with the shoulder feature of the second fin;   forming an insulating layer comprising nitrogen, the insulating layer directly on the layer comprising the PSG;   forming a dielectric fill material directly laterally adjacent to the insulating layer; and   forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin.   
     
     
         2 . The method of  claim 1 , wherein the lower fin portion of the first fin has a width different than a width of the upper fin portion of the first fin at the region between the lower fin portion and the upper fin portion of the first fin, and wherein the lower fin portion of the second fin has a width different than a width of the upper fin portion of the second fin at the region between the lower fin portion and the upper fin portion of the second fin. 
     
     
         3 . The method of  claim 2 , wherein the width of the lower fin portion of the first fin is less than the width of the upper fin portion of the first fin, and wherein the width of the lower fin portion of the second fin is less than the width of the upper fin portion of the second fin. 
     
     
         4 . The method of  claim 1 , wherein the layer comprising the PSG has a phosphorous concentration in the range of 0.1-10 weight %. 
     
     
         5 . A method of fabricating an integrated structure, the method comprising:
 forming a first fin comprising a silicon material, the first fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;   forming a second fin comprising the silicon material, the second fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion;   forming a dielectric layer comprising an N-type dopant, the dielectric layer directly on sidewalls of the lower fin portion of the first fin and directly on sidewalls of the lower fin portion of the second fin, the dielectric layer having a first end portion substantially co-planar with the shoulder feature of the first fin, and the dielectric layer having a second end portion substantially co-planar with the shoulder feature of the second fin;   forming an insulating layer comprising nitrogen, the insulating layer directly on the dielectric layer;   forming a dielectric fill material directly laterally adjacent to the insulating layer; and   forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin.   
     
     
         6 . The method of  claim 5 , wherein the lower fin portion of the first fin has a width different than a width of the upper fin portion of the first fin at the region between the lower fin portion and the upper fin portion of the first fin, and wherein the lower fin portion of the second fin has a width different than a width of the upper fin portion of the second fin at the region between the lower fin portion and the upper fin portion of the second fin. 
     
     
         7 . The method of  claim 6 , wherein the width of the lower fin portion of the first fin is less than the width of the upper fin portion of the first fin, and wherein the width of the lower fin portion of the second fin is less than the width of the upper fin portion of the second fin. 
     
     
         8 . The method of  claim 5 , wherein the Ntype dopant is phosphorous, and wherein the dielectric layer has a phosphorous concentration in the range of 0.1-10 weight %. 
     
     
         9 . The method of  claim 5 , wherein the Ntype dopant is arsenic, and wherein the dielectric layer has an arsenic concentration in the range of 0.1-10 weight %. 
     
     
         10 . A method of fabricating a computing device, the method comprising:
 providing a board; and   coupling a component coupled to the board, the component including an integrated circuit structure, comprising:
 forming a first fin comprising a silicon material, the first fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion; 
 forming a second fin comprising the silicon material, the second fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion; 
 forming a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly on sidewalls of the lower fin portion of the first fin and directly on sidewalls of the lower fin portion of the second fin, the layer comprising the PSG having a first end portion substantially co-planar with the shoulder feature of the first fin, and the layer comprising the PSG having a second end portion substantially co-planar with the shoulder feature of the second fin; 
 forming an insulating layer comprising nitrogen, the insulating layer directly on the layer comprising the PSG; 
 forming a dielectric fill material directly laterally adjacent to the insulating layer; and 
   forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin.   
     
     
         11 . The method of  claim 10 , further comprising:
 coupling a memory coupled to the board.   
     
     
         12 . The method of  claim 10 , further comprising:
 coupling a communication chip coupled to the board.   
     
     
         13 . The method of  claim 10 , further comprising:
 coupling a camera coupled to the board.   
     
     
         14 . The method of  claim 10 , further comprising:
 coupling a battery coupled to the board.   
     
     
         15 . The method of  claim 10 , further comprising:
 coupling an antenna coupled to the board.   
     
     
         16 . The method of  claim 10 , wherein the component is a packaged integrated circuit die. 
     
     
         17 . A method of fabricating a computing device, the method comprising:
 providing a board; and   coupling a component coupled to the board, the component including an integrated circuit structure, comprising:
 forming a first fin comprising a silicon material, the first fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion; 
 forming a second fin comprising the silicon material, the second fin having a lower fin portion and an upper fin portion and a shoulder feature at a region between the lower fin portion and the upper fin portion; 
 forming a dielectric layer comprising an N-type dopant, the dielectric layer directly on sidewalls of the lower fin portion of the first fin and directly on sidewalls of the lower fin portion of the second fin, the dielectric layer having a first end portion substantially coplanar with the shoulder feature of the first fin, and the dielectric layer having a second end portion substantially co-planar with the shoulder feature of the second fin; 
 forming an insulating layer comprising nitrogen, the insulating layer directly on the dielectric layer; 
 forming a dielectric fill material directly laterally adjacent to the insulating layer; and 
 forming a gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, and the gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the second fin, and the gate electrode over the dielectric fill material between the first fin and the second fin. 
   
     
     
         18 . The method of  claim 17 , further comprising:
 coupling a memory coupled to the board.   
     
     
         19 . The method of  claim 17 , further comprising:
 coupling a communication chip coupled to the board.   
     
     
         20 . The method of  claim 17 , further comprising:
 coupling a camera coupled to the board.   
     
     
         21 . The method of  claim 17 , further comprising:
 coupling a battery coupled to the board.   
     
     
         22 . The method of  claim 17 , further comprising:
 coupling an antenna coupled to the board.   
     
     
         23 . The method of  claim 17 , wherein the component is a packaged integrated circuit die.