Semiconductor devices including support pattern and methods of fabricating the same

Abstract

Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of word lines in a substrate and parallel to each other;   a plurality of first impurity regions and a plurality of second impurity regions in the substrate, wherein one of the plurality of first impurity regions and the plurality of second impurity regions is between two adjacent word lines of the plurality of word lines, and the plurality of first impurity regions and the plurality of second impurity regions are spaced apart from each other;   a plurality of bottom electrodes on the substrate and electrically connected to the plurality of first impurity regions, respectively;   a plurality of storage node contacts, wherein each of the plurality of storage node contacts electrically connects a respective one of the plurality of bottom electrodes to a respective one of the plurality of first impurity regions;   a plurality of landing pads, wherein each of the plurality of landing pads is between a respective one of the plurality of storage node contacts and a respective one of the plurality of bottom electrodes;   a plurality of bit lines on the substrate and electrically connected to the plurality of second impurity regions, respectively, the plurality of bit lines crossing over the plurality of word lines;   a plurality of bit-line contacts between a respective one of the plurality of bit lines and a respective one of the plurality of second impurity regions; and   a support pattern in contact with a first portion of a sidewall of each of the plurality of bottom electrodes,   wherein:
 the support pattern includes a plurality of support holes, and a second portion of the sidewall of each of the plurality of bottom electrodes defines a respective one of the plurality of support holes, 
 the plurality of support holes include a first support hole and a second support hole that are spaced apart from each other, 
 when viewed in plan, the support pattern comprises first inner sidewalls that define the first support hole and define a circumference of a circle, and 
 when viewed in plan, the support pattern comprises second inner sidewalls that define the second support hole and define, respectively, sides of a triangle. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first support hole comprises three first support holes and the second support hole comprises three second support holes, and the three first support holes and the three second support holes are spaced apart from each other and arranged in an alternating sequence around a center of a hexagon, and
 wherein centers of the three first support holes and the three second support holes overlap, respectively, vertices of the hexagon.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the plurality of bottom electrodes comprise three bottom electrodes that are adjacent to each other, and the three bottom electrodes define the first support hole of the plurality of support holes. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising bit-line spacers on respective sidewalls of the plurality of bit lines,
 wherein each of the bit-line spacers includes a first sub-spacer and a second sub-spacer that are spaced apart from each other by a gap region between the first sub-spacer and the second sub-spacer.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the plurality of support holes further include a third support hole, and the triangle is a first triangle,
 wherein, when viewed in plan, the support pattern comprises third inner sidewalls that define the third support hole and define, respectively, sides of a second triangle, and   wherein, when viewed in plan, the second support hole and the third support hole have different respective shapes.   
     
     
         6 . The semiconductor device of  claim 5 , wherein, when viewed in plan, the first, second, and third support holes are immediately adjacent to each other and arranged along a first direction, and the first support hole is between the second support hole and the third support hole. 
     
     
         7 . The semiconductor device of  claim 1 , further comprising a plurality of separation dielectric patterns, wherein one of the plurality of separation dielectric patterns is interposed between two adjacent landing pads of the plurality of landing pads, and
 wherein top surfaces of the plurality of separation dielectric patterns are coplanar with top surfaces of the plurality of landing pads.   
     
     
         8 . A semiconductor device comprising:
 a plurality of vertical structures on a substrate; and   a support pattern that contacts sidewalls of the plurality of vertical structures,   wherein the support pattern comprises a plurality of support holes extending through the support pattern,   wherein the plurality of support holes comprise a first support hole and a second support hole that are spaced apart from each other,   wherein the first support hole has a shape in plan view of a first triangle in which a first subset of three of the plurality of vertical structures are on respective vertices of the first triangle, and wherein the second support hole has a shape in plan view of a second triangle in which a second subset of three of the plurality of vertical structures are on respective edges of the second triangle.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the plurality of support holes further comprise a third support hole, and
 wherein the third support hole has a shape in plan view of a circle in which a third subset of the plurality of vertical structures are around a perimeter of the circle.   
     
     
         10 . The semiconductor device of  claim 9 , wherein a plurality of the first support holes and a plurality of the second support holes are arranged in an alternating sequence around the third support hole. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the plurality of the first support holes and the plurality of the second support holes are arranged in the alternating sequence around a center of a hexagon, and
 wherein centers of the plurality of the first support holes and the plurality of the second support holes overlap, respectively, vertices of the hexagon.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the third support hole is at the center of the hexagon. 
     
     
         13 . The semiconductor device of  claim 8 , wherein, when viewed in plan view, the support pattern extends on a vertex of the second triangle of the second support hole. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the vertex of the second triangle of the second support hole extends between two vertical structures of the second subset of three of the plurality of vertical structures.