Circuits and methods for wake-up receivers

Abstract

Circuit for wake-up receivers are provide. In some embodiments, the wake-up receivers include self-mixers that receive a gate bias voltage. Some of the self-mixers are single ended and some are differential. In some embodiments, the wake-up receivers include a matching network that is connected to the input of the self-mixer. In some embodiments, the wake-up receivers include a low frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers include a high frequency path connected to the output of the self-mixer. In some embodiments, the wake-up receivers are configured to receive an encoded bit stream. In some embodiments, the wake-up receivers are configured to wake-up another receiver.

What is claimed is: 
     
         1 . A circuit for a wake-up receiver comprising:
 a first self-mixer stage comprising:
 a first NMOS transistor having a source, a drain, and a gate; 
 a second NMOS transistor having a source, a drain, and a gate, wherein the drain of the second NMOS transistor is connected to the drain of the first NMOS transistor; 
 a first PMOS transistor having a source, a drain, and a gate, wherein the source of the first PMOS transistor is connected to the source of the first NMOS transistor; 
 a second PMOS transistor having a source, a drain, and a gate, wherein the drain of the second PMOS transistor is connected to the drain of the first PMOS transistor, and the source of the second PMOS transistor is connected to the source of the second NMOS transistor; 
 a first resistor having a first side connected to the gate of the first NMOS transistor and having a second side connected to a first gate bias voltage; 
 a second resistor having a first side connected to the gate of the first PMOS transistor and having a second side connected to a second gate bias voltage; 
 a third resistor having a first side connected to the gate of the second NMOS transistor and having a second side connected to the first gate bias voltage; 
 a fourth resistor having a first side connected to the gate of the second PMOS transistor and having a second side connected to the second gate bias voltage; 
 a first coupling capacitor having a first side connected to a first radio frequency (RF) input signal and having a second side connected to the gate of the first NMOS transistor; 
 a second coupling capacitor having a first side connected to the first RF input signal and having a second side connected to the gate of the first PMOS transistor; 
 a third coupling capacitor having a first side connected to a second RF input signal and having a second side connected to the gate of the second NMOS transistor; and 
 a fourth coupling capacitor having a first side connected to the second RF input signal and having a second side connected to the gate of the second PMOS transistor. 
   
     
     
         2 . The circuit of  claim 1 , wherein the first self-mixer stage further comprises:
 a fifth coupling capacitor having a first side connected to the source of the first NMOS transistor having a second side connected to the second RF input signal; and   a sixth coupling capacitor having a first side connected to the source of the second NMOS transistor and having a second side connected to the first RF input signal.   
     
     
         3 . The circuit of  claim 1 , wherein the drain of the first PMOS transistor is connected to a common mode voltage. 
     
     
         4 . The circuit of  claim 1 , wherein the first RF input signal is an inverted form of the second RF input signal. 
     
     
         5 . The circuit of  claim 1 , further comprising a second self-mixer stage. 
     
     
         6 . The circuit of  claim 1 , further comprising a matching network that provides the first RF input signal and the second RF input signal. 
     
     
         7 . The circuit of  claim 1 , wherein the drain of the first NMOS transistor provides a first output signal and the drain of the first PMOS transistor provides a second output signal. 
     
     
         8 . The circuit of  claim 7 , further comprising a low-pass filter having a first input connected to the first output signal, having a second input connected to the second output signal, having a first output, and having a second output. 
     
     
         9 . The circuit of  claim 8 , further comprising a first hysteresis comparator having a first input connected to the first output of the low pass filter, having a second input connected to the second output of the low pass filter, having a first output, and having a second output. 
     
     
         10 . The circuit of  claim 9 , further comprising a first correlator having a first input connected to the first output of the first hysteresis comparator and having a first output. 
     
     
         11 . The circuit of  claim 8 , further comprising a high pass filter having a first output connected to the first output signal and having a second input connected to the second output signal. 
     
     
         12 . The circuit of  claim 11 , further comprising a second hysteresis comparator having a first input connected to the first output of the high pass filter, having a second input connected to the second output of the high pass filter, having a first output, and having a second output. 
     
     
         13 . The circuit of  claim 12 , further comprising a first envelope detector connected to the first output of the second hysteresis comparator and a second envelope detector connected to the second output of the second hysteresis comparator. 
     
     
         14 . The circuit of  claim 13 , further comprising a second correlator having a first input connected to the first output of the second hysteresis comparator and having a first output. 
     
     
         15 . The circuit of  claim 14 , further comprising an adder connected to the first output of the second correlator. 
     
     
         16 . The circuit of  claim 14 , wherein the second correlator receives a Barker code. 
     
     
         17 . The circuit of  claim 16 , wherein the Barker code is 11 bits.