Embedded memory employing self-aligned top-gated thin film transistors

Abstract

Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

What is claimed is: 
     
         1 . An integrated circuit (IC) device, comprising:
 a first capacitor electrically coupled to a first terminal of a first thin film transistor at a first circuit node;   a second capacitor electrically coupled to a first terminal of a second thin film transistor at a second circuit node;   a third thin film transistor having a first terminal electrically coupled to the first circuit node, and a second terminal electrically coupled to the second circuit node, wherein the terminals of the first, second, and third thin film transistors comprise portions of a continuous layer of a semiconductor material comprising oxygen;   bit-cell addressing lines coupled to a second terminal and a gate terminal of the first and second transistors; and   a bit-cell isolation biasing line coupled to a gate terminal of the third transistor.   
     
     
         2 . The IC device of  claim 1 , wherein the bit-cell addressing lines comprise:
 a first wordline electrically coupled to a gate terminal of the first thin film transistor;   a second wordline electrically coupled to a gate terminal of the second thin film transistor; and   a bitline electrically coupled to a second terminal of the first thin film transistor, and electrically coupled to a second terminal of the second thin film transistor.   
     
     
         3 . The IC device of  claim 2 , wherein first and second terminals of all thin film transistors electrically coupled to the bitline comprise portions of a continuous stripe of the semiconductor material, the strip having a longest length along a direction parallel to the bitline. 
     
     
         4 . The IC device of  claim 3 , wherein the bitline is one of a plurality of bitlines and the continuous stripe of the semiconductor material is one of a plurality of stripes of the semiconductor material crossed by the first wordline and the second wordline, and individual ones of the plurality of stripes of the semiconductor material comprise thin film transistors coupled to individual ones of the bitlines. 
     
     
         5 . The IC device of  claim 1 , wherein:
 the bit-cell addressing lines comprise:
 a first wordline electrically coupled to a first wordline driver operable to bias the gate terminal of the first thin film transistor to a positive voltage; 
 a second wordline electrically coupled to a second wordline driver operable to bias the gate terminal of the second thin film transistor to the positive voltage; and 
   the bit-cell isolation biasing line is electrically coupled to a third wordline driver operable to maintain a negative voltage on the gate terminal of the third thin film transistor while the first and second wordlines are biased to the positive voltage.   
     
     
         6 . The IC device of  claim 1 , wherein the first, second and third thin film transistors comprise a gate dielectric between the gate terminals and the semiconductor material comprising oxygen. 
     
     
         7 . The IC device of  claim 6 , wherein the semiconductor material comprising oxygen is amorphous or polycrystalline 
     
     
         8 . The IC device of  claim 6 , wherein the semiconductor material comprises indium, gallium, and zinc. 
     
     
         9 . The IC device of  claim 1 , further comprising row circuitry and column circuitry comprising a plurality of field effect transistors (FETs) at least partially below the first, second and third thin film transistors, wherein the bit-cell addressing lines are electrically coupled to the row circuitry and the column circuitry through one or more levels of metallization between the plurality of FETs and the first, second and third thin film transistors. 
     
     
         10 . A system comprising:
 one or more processors; and   a memory device coupled to the processors, wherein the memory device comprises:
 a memory array, comprising:
 a first capacitor electrically coupled to a first terminal of a first thin film transistor at a first circuit node; 
 a second capacitor electrically coupled to a first terminal of a second thin film transistor at a second circuit node; 
 a third thin film transistor having a first terminal electrically coupled to the first circuit node, and a second terminal electrically coupled to the second circuit node, wherein the terminals of the first, second, and third thin film transistors comprise portions of a continuous layer of a semiconductor material comprising oxygen; 
 bit-cell addressing lines coupled to a second terminal and a gate terminal of the first and second transistors; and 
 a bit-cell isolation biasing line coupled to a gate terminal of the third transistor; and 
 
 memory circuitry coupled to the memory array, wherein the memory circuitry comprises a plurality of drivers coupled to the bit-cell addressing lines through one or more metallization levels, wherein the drivers comprise a plurality of field effect transistors (FETs) that are at least partially under the memory array. 
   
     
     
         11 . The system of  claim 10 , wherein individual ones of the FETs comprise a monocrystalline semiconductor channel material. 
     
     
         12 . The system of  claim 10 , wherein:
 the bit-cell addressing lines comprise:
 a first wordline electrically coupled to a first wordline driver operable to bias the gate terminal of the first thin film transistor to a positive voltage; 
 a second wordline electrically coupled to a second wordline driver operable to bias the gate terminal of the second thin film transistor to the positive voltage; and 
   the bit-cell isolation biasing line is electrically coupled to a third wordline driver operable to maintain a negative voltage on the gate terminal of the third thin film transistor while the first and second wordlines are biased to the positive voltage.   
     
     
         13 . The system of  claim 10 , wherein the one or more levels of metallization are between the plurality of FETs and the thin film transistors. 
     
     
         14 . The system of  claim 10 , wherein the first, second and third thin film transistors comprise a gate dielectric between the gate terminals and the semiconductor material. 
     
     
         15 . The system of  claim 14 , wherein the semiconductor material is amorphous or polycrystalline and comprises indium, gallium, and zinc. 
     
     
         16 . A method comprising:
 forming stripes of a thin film semiconductor material comprising oxygen, the film semiconductor material stripes extending in a first dimension over peripheral circuitry comprising a plurality of field effect transistors (FETs);   forming gate terminal stripes in a second dimension and crossing the thin film semiconductor material stripes;   forming a first capacitor electrically coupled to a first terminal of a first thin film transistor at a first circuit node;   forming a second capacitor electrically coupled to a first terminal of a second thin film transistor at a second circuit node;   forming a third thin film transistor having a first terminal electrically coupled to the first circuit node, and a second terminal electrically coupled to the second circuit node, wherein the terminals of the first, second, and third thin film transistors comprise contiguous portions of one of the thin film semiconductor material stripes; and   coupling wordline drivers of the peripheral circuitry to the gate terminal stripes of the first and second transistors; and   coupling an electrical isolation biasing driver of the peripheral circuitry to the gate terminal stripe of the third transistor.   
     
     
         17 . The method of  claim 16 , further comprising forming the FETs with a monocrystalline semiconductor channel. 
     
     
         18 . The method of  claim 16 , further comprising forming one or more levels of metallization between the FETs and the thin film semiconductor stripes. 
     
     
         19 . The method of  claim 17 , wherein forming one or more levels of metallization further comprises forming metallization lines that extend in the second dimension under the thin film semiconductor material stripes and aligned below corresponding ones of the gate terminal stripes. 
     
     
         20 . The method of  claim 19 , wherein forming the levels of metallization further comprises coupling individual ones of the gate terminal stripes to corresponding ones of metallization lines at multiple points over a length of the gate terminal stripes.