Semiconductor device

Abstract

The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor; and   a fourth transistor,   wherein the third transistor is provided over the first transistor and the second transistor,   wherein a first channel formation region of the first transistor comprises silicon,   wherein a second channel formation region of the second transistor comprises silicon,   wherein a third channel formation region of the third transistor comprises an oxide semiconductor,   wherein a fourth channel formation region of the fourth transistor comprises an oxide semiconductor,   wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,   wherein a first insulating layer is provided over the first channel formation region,   wherein a first gate electrode is provided over the first insulating layer,   wherein a second insulating layer is provided over the third channel formation region,   wherein a second gate electrode is provided over the second insulating layer, and   wherein a third insulating layer is provided over the second gate electrode.   
     
     
         3 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor;   a fourth transistor; and   a first capacitor,   wherein the third transistor is provided over the first transistor and the second transistor,   wherein a first channel formation region of the first transistor comprises silicon,   wherein a second channel formation region of the second transistor comprises silicon,   wherein a third channel formation region of the third transistor comprises an oxide semiconductor,   wherein a fourth channel formation region of the fourth transistor comprises an oxide semiconductor,   wherein one of a source and a drain of the third transistor is electrically connected to a first gate electrode of the first transistor and to one electrode of the first capacitor,   wherein a first insulating layer is provided over the first channel formation region,   wherein the first gate electrode is provided over the first insulating layer,   wherein a second insulating layer is provided over the third channel formation region,   wherein a second gate electrode is provided over the second insulating layer,   wherein a third insulating layer is provided over the second gate electrode, and   wherein the other of the source and the drain of the third transistor is provided over the third insulating layer.   
     
     
         4 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor;   a fourth transistor;   a first capacitor; and   a second capacitor,   wherein the third transistor is provided over the first transistor and the second transistor,   wherein a first channel formation region of the first transistor comprises silicon,   wherein a second channel formation region of the second transistor comprises silicon,   wherein a third channel formation region of the third transistor comprises an oxide semiconductor,   wherein a fourth channel formation region of the fourth transistor comprises an oxide semiconductor,   wherein one of a source and a drain of the third transistor is electrically connected to a first gate electrode of the first transistor and to one electrode of the first capacitor,   wherein one of a source and a drain of the fourth transistor is electrically connected to one electrode of the second transistor,   wherein a first insulating layer is provided over the first channel formation region,   wherein the first gate electrode is provided over the first insulating layer,   wherein a second insulating layer is provided over the third channel formation region,   wherein a second gate electrode is provided over the second insulating layer, and   wherein a third insulating layer is provided over the second gate electrode.   
     
     
         5 . The semiconductor device according to  claim 2 ,
 wherein the second insulating layer is in contact with a side surface of the other of the source and the drain of the third transistor.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein the second insulating layer is in contact with a side surface of the other of the source and the drain of the third transistor.   
     
     
         7 . The semiconductor device according to  claim 4 ,
 wherein the second insulating layer is in contact with a side surface of the other of the source and the drain of the third transistor.   
     
     
         8 . The semiconductor device according to  claim 2 ,
 wherein the one of the source and the drain of the third transistor is directly connected to the one of the source and the drain of the fourth transistor.   
     
     
         9 . The semiconductor device according to  claim 2 ,
 wherein a third gate electrode of the fourth transistor is provided over the second insulating layer.   
     
     
         10 . The semiconductor device according to  claim 3 ,
 wherein a third gate electrode of the fourth transistor is provided over the second insulating layer.   
     
     
         11 . The semiconductor device according to  claim 4 ,
 wherein a third gate electrode of the fourth transistor is provided over the second insulating layer.   
     
     
         12 . The semiconductor device according to  claim 3 ,
 wherein the other electrode of the first capacitor is provided over the second insulating layer.   
     
     
         13 . The semiconductor device according to  claim 2 ,
 wherein the fourth transistor is provided over the first transistor and second transistor.   
     
     
         14 . The semiconductor device according to  claim 3 ,
 wherein the fourth transistor is provided over the first transistor and second transistor.   
     
     
         15 . The semiconductor device according to  claim 4 ,
 wherein the fourth transistor is provided over the first transistor and second transistor.   
     
     
         16 . The semiconductor device according to  claim 2 ,
 wherein the third channel formation region and the fourth channel formation region are provided in a same island-shaped oxide semiconductor layer.   
     
     
         17 . The semiconductor device according to  claim 3 ,
 wherein the third channel formation region and the fourth channel formation region are provided in a same island-shaped oxide semiconductor layer.   
     
     
         18 . The semiconductor device according to  claim 4 ,
 wherein the third channel formation region and the fourth channel formation region are provided in a same island-shaped oxide semiconductor layer.   
     
     
         19 . The semiconductor device according to  claim 16 ,
 wherein the oxide semiconductor layer comprises indium, gallium, and zinc,   wherein the oxide semiconductor layer comprises a crystalline portion, and   wherein the first channel formation region and the second channel formation region comprise polycrystalline silicon.   
     
     
         20 . The semiconductor device according to  claim 17 ,
 wherein the oxide semiconductor layer comprises indium, gallium, and zinc,   wherein the oxide semiconductor layer comprises a crystalline portion, and   wherein the first channel formation region and the second channel formation region comprise polycrystalline silicon.   
     
     
         21 . The semiconductor device according to  claim 18 ,
 wherein the oxide semiconductor layer comprises indium, gallium, and zinc,   wherein the oxide semiconductor layer comprises a crystalline portion, and   wherein the first channel formation region and the second channel formation region comprise polycrystalline silicon.