On-demand binary translation state map generation

Abstract

A disclosed example includes generating a binary translation of a native code section in response to a determination that the binary translation of the native code section is not present in a translation cache; storing the binary translation of the native code section in the translation cache; determining that a stop has occurred during the generation of the binary translation; subsequent to the determination that the stop has occurred, generating a binary translation state map of at least a portion of the binary translation; storing, for at least a portion of a duration of the stop, the binary translation state map in memory; and discarding the binary translation state map from the memory upon termination of the stop, the binary translation state map to not exist after the discard of the binary translation state map.

What is claimed: 
     
         1 . A device comprising:
 processor circuitry to execute a native code section; and   binary translation circuitry to:
 generate a binary translation of the native code section in response to a determination that the binary translation of the native code section is not present in a translation cache; 
 store the binary translation of the native code section in the translation cache; 
 determine that a stop has occurred during the generation of the binary translation; 
 subsequent to the determination that the stop has occurred, generate a binary translation state map of at least a portion of the binary translation; 
 store, for at least a portion of a duration of the stop, the binary translation state map in memory; and 
 discard the binary translation state map from the memory upon termination of the stop, the binary translation state map to not exist after the discard of the binary translation state map. 
   
     
     
         2 . The device of  claim 1 , wherein the binary translation circuitry is to store a start address of the native code section and a region formation strategy used to generate the binary translation. 
     
     
         3 . The device of  claim 2 , wherein the binary translation circuitry is to generate the binary translation state map based on the start address and the region formation strategy. 
     
     
         4 . The device of  claim 1 , wherein the stop is caused by the binary translation circuitry determining that an exception or a code modification in a section of native code has occurred. 
     
     
         5 . The device of  claim 1 , wherein in response to detection of a code modification in a section of native code, the binary translation circuitry is to determine if the code modification affects execution of the binary translation. 
     
     
         6 . The device of  claim 1 , wherein in generating the binary translation state map, the binary translation circuitry is to:
 determine a stop location and offset in the binary translation;   form a region from native code based at least on the stop location;   load instructions from the region;   determine the binary translation state map based at least on a size of the loaded instructions; and   
       map to a location in the native code by applying the offset to the binary translation state map. 
     
     
         7 . The device of  claim 6 , wherein the binary translation circuitry does not translate ones of the loaded instructions into binary code when generating the binary translation state map. 
     
     
         8 . At least one non-transitory computer readable medium comprising instructions that, when executed, cause one or more processors to at least:
 generate a binary translation of a native code section in response to a determination that the binary translation of the native code section is not present in a translation cache;   store the binary translation of the native code section in the translation cache;   determine that a stop has occurred during the generation of the binary translation;   subsequent to the determination that the stop has occurred, generate a binary translation state map of at least a portion of the binary translation;   store, for at least a portion of a duration of the stop, the binary translation state map in memory; and   discard the binary translation state map from the memory upon termination of the stop, the binary translation state map to not exist after the discard of the binary translation state map.   
     
     
         9 . The at least one non-transitory computer readable medium of  claim 8 , wherein the instructions are to cause the one or more processors to store a start address of the native code section and a region formation strategy used to generate the binary translation. 
     
     
         10 . The at least one non-transitory computer readable medium of  claim 9 , wherein the instructions are to cause the one or more processors to generate the binary translation state map based on the start address and the region formation strategy. 
     
     
         11 . The at least one non-transitory computer readable medium of  claim 8 , wherein the stop is caused based on a determination that an exception or a code modification in a section of native code has occurred. 
     
     
         12 . The at least one non-transitory computer readable medium of  claim 8 , wherein in response to detection of a code modification in a section of native code, the instructions are to cause the one or more processors to determine if the code modification affects execution of the binary translation. 
     
     
         13 . The at least one non-transitory computer readable medium of  claim 8 , wherein in generating the binary translation state map, the instructions are to cause the one or more processors to:
 determine a stop location and offset in the binary translation;   form a region from native code based at least on the stop location;   load instructions from the region;   determine the binary translation state map based at least on a size of the loaded instructions; and   map to a location in the native code by applying the offset to the binary translation state map.   
     
     
         14 . The at least one non-transitory computer readable medium of  claim 13 , wherein the instructions are to cause the one or more processors to not translate ones of the loaded instructions into binary code when generating the binary translation state map. 
     
     
         15 . A method comprising:
 generating, by executing an instruction with a processor, a binary translation of a native code section in response to a determination that the binary translation of the native code section is not present in a translation cache;   storing, by executing an instruction with the processor, the binary translation of the native code section in the translation cache;   determining, by executing an instruction with the processor, that a stop has occurred during the generation of the binary translation;   subsequent to the determination that the stop has occurred, generating, by executing an instruction with the processor, a binary translation state map of at least a portion of the binary translation;   storing, by executing an instruction with the processor and for at least a portion of a duration of the stop, the binary translation state map in memory; and   discarding, by executing an instruction with the processor, the binary translation state map from the memory upon termination of the stop, the binary translation state map to not exist after the discard of the binary translation state map.   
     
     
         16 . The method of  claim 15 , further including storing a start address of the native code section and a region formation strategy used to generate the binary translation. 
     
     
         17 . The method of  claim 16 , wherein the generating of the binary translation state map is based on the start address and the region formation strategy. 
     
     
         18 . The method of  claim 15 , wherein the stop is caused based on a determination that an exception or a code modification in a section of native code has occurred. 
     
     
         19 . The method of  claim 15 , further including, in response to detection of a code modification in a section of native code, determining if the code modification affects execution of the binary translation. 
     
     
         20 . The method of  claim 15 , wherein in generating the binary translation state map, the method further includes:
 determining a stop location and offset in the binary translation;   forming a region from native code based at least on the stop location;   loading instructions from the region;   determining the binary translation state map based at least on a size of the loaded instructions; and   mapping to a location in the native code by applying the offset to the binary translation state map.