Machine learning hardware accelerator

Abstract

In a memory device, a static random access memory (SRAM) circuit includes an array of SRAM cells arranged in rows and columns and configured to store data. The SRAM array is configured to: store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells. A memory controller circuit is configured to select the set of the SRAM cells based on a second set of information for the ML process.

What is claimed is: 
     
         1 . A memory device, comprising:
 a static random access memory (SRAM) circuit including an array of SRAM cells arranged in rows and columns and configured to store data, the SRAM array configured to:
 store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and 
 consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells; and 
   a memory controller circuit configured to select the set of the SRAM cells based on a second set of information for the ML process.   
     
     
         2 . The memory device of  claim 1 , further comprising:
 a first switch circuit configured to select a column of the lookup table based on a bit value from the second set of information; and   a first accumulator circuit configured to: receive the information accessed from the selected set of the SRAM cells; and perform a first bitwise addition and shift on first bits of the received information as the first bits are consecutively accessed.   
     
     
         3 . The memory device of  claim 2 , further comprising:
 a second switch circuit configured to select a column of the lookup table based on a bit value from a third set of information; and   a second accumulator circuit configured to: receive the information accessed from the selected set of the SRAM cells; and perform a second bitwise addition and shift on second bits of the received information as the second bits are consecutively accessed.   
     
     
         4 . The memory device of  claim 3 , wherein the first and second accumulator circuits include a set of 1-bit full adders. 
     
     
         5 . The memory device of  claim 1 , wherein the first set of information is based on one or more weights applicable to the ML process, and the second set of information includes input data for the ML process. 
     
     
         6 . The memory device of  claim 1 , wherein the first set of information includes input data for the ML process, and the second set of information is based on one or more weights applicable to the ML process. 
     
     
         7 . The memory device of  claim 6 , further comprising a circuit configured to compute a set of possible results based on the input data. 
     
     
         8 . A system, comprising:
 one or more microprocessors coupled to a memory circuit, the memory circuit including:   a static random access memory (SRAM) circuit including an array of SRAM cells arranged in rows and columns and configured to store data, the SRAM array configured to:   store a first set of information for a machine learning (ML) process in a lookup table in the SRAM array; and   consecutively access, from the lookup table, information from a selected set of the SRAM cells along a row of the SRAM cells; and   a memory controller circuit configured to select the set of the SRAM cells based on a second set of information for the ML process.   
     
     
         9 . The system of  claim 8 , wherein the memory circuit includes:
 a first switch circuit configured to select a column of the lookup table based on a bit value from the second set of information; and   a first accumulator circuit configured to: receive the information accessed from the selected set of the SRAM cells; and perform a first bitwise addition and shift on first bits of the received information as the first bits are consecutively accessed.   
     
     
         10 . The system of  claim 9 , wherein the memory circuit includes:
 a second switch circuit configured to select a column of the lookup table based on a bit value from a third set of information; and   a second accumulator circuit configured to: receive the information accessed from the selected set of the SRAM cells; and perform a second bitwise addition and shift on second bits of the received information as the second bits are consecutively accessed.   
     
     
         11 . The system of  claim 10 , wherein the first and second accumulator circuits include a set of 1-bit full adders. 
     
     
         12 . The system of  claim 8 , wherein the first set of information is based on one or more weights applicable to the ML process, and the second set of information includes input data for the ML process. 
     
     
         13 . The system of  claim 8 , wherein the first set of information includes input data for the ML process, and the second set of information is based on one or more weights applicable to the ML process. 
     
     
         14 . The system of  claim 13 , wherein the memory circuit includes a circuit configured to compute a set of possible results based on the input data. 
     
     
         15 . A method, comprising:
 receiving a first set of information for a machine learning (ML) process;   storing the first set of information in a lookup table in an array of SRAM cells, the SRAM cells arranged in rows and columns;   selecting a set of the SRAM cells based on a second set of information for the ML process; and   consecutively accessing, from the lookup table, information from the selected set of the SRAM cells along a row of the SRAM cells.   
     
     
         16 . The method of  claim 15 , further comprising:
 selecting a column of the lookup table based on a bit value from the second set of information;   receiving the information accessed from the selected set of the SRAM cells; and   performing a first bitwise addition and shift on first bits of the received information as the first bits are consecutively accessed.   
     
     
         17 . The method of  claim 16 , further comprising:
 selecting a column of the lookup table based on a bit value from a third set of information;   receiving the information accessed from the selected set of the SRAM cells; and   performing a second bitwise addition and shift on second bits of the received information as the second bits are consecutively accessed.   
     
     
         18 . The method of  claim 15 , wherein the first set of information is based on one or more weights applicable to the ML process, and the second set of information includes input data for the ML process. 
     
     
         19 . The method of  claim 15 , wherein the first set of information includes input data for the ML process, and the second set of information is based on one or more weights applicable to the ML process. 
     
     
         20 . The method of  claim 19 , further comprising precomputing a set of possible results based on the input data.