Time to Live for Memory Access by Processors

Abstract

Systems, apparatuses, and methods to implement time to live for memory access by processors. For example, a processor has a register configured to store a parameter specifying a time duration indicative of the desired time to live. A memory system has multiple components with different latencies for memory access. When the memory controller of the processor sends a command to the memory system to load an item from a memory address, the memory system can fail to provide, to the processor within the time duration, the item from the memory address currently being hosted in a first component. In response, the memory controller can send a signal to abort the command; and the memory system can select a second component having a memory access latency shorter than the first component, and change the hosting of the memory address from in the first component to in the second component.

What is claimed is: 
     
         1 . A processor, comprising:
 a register operable to store a parameter representative of a time duration;   a plurality of execution units; and   a memory controller;   wherein during execution of an instruction in the processor to load a data item from a memory system, the memory controller is configured to send a command to the memory system;   wherein in response to a determination that the memory system fails to respond to the command within the time duration identified by the register, the memory controller is configured to send a signal to the memory system to abort the command.   
     
     
         2 . The processor of  claim 1 , wherein the command is configured to request the memory system to retrieve the data item from a memory address; and the signal is configured to cause the memory system to identify a latency for retrieval of the data item, and remap the memory address to store the data item for retrieval according to the latency identified in response to the signal. 
     
     
         3 . The processor of  claim 2 , wherein the memory system is configured to have a plurality of memory components having different latencies for data retrieval; and the time duration identified by the register is shorter than a data retrieval latency of at least one of the plurality of memory components. 
     
     
         4 . The processor of  claim 3 , wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof. 
     
     
         5 . The processor of  claim 2 , wherein prior to the signal, the memory address is mapped to a first memory component in the memory system to store the data item; and the signal is configured to identify the latency in combination with the command to cause the memory system to identify a second memory component in the memory system to store the data item for the memory address. 
     
     
         6 . The processor of  claim 5 , wherein the memory controller is further configured to resend, after at least a predetermined period of time following the signal, the command to the memory system. 
     
     
         7 . The processor of  claim 6 , wherein the predetermined period of time is configured to be longer than a time period for the memory system to remap the memory address from the first memory component to the second memory component. 
     
     
         8 . The processor of  claim 6 , wherein the memory controller is further configured to:
 free a resource associated with the command after sending the signal; and   perform an operation using the resource between sending the signal and resending the command.   
     
     
         9 . The processor of  claim 6 , wherein the memory controller is further configured to send, after sending the signal and before resending the command, a further command to retrieve data from an address different from the memory address. 
     
     
         10 . A memory system, comprising:
 a plurality of memory components having different latencies in data retrieval; and   a controller coupled to the plurality of memory components and configured to:
 receive a command from a processor to load a data item from a memory address; 
 execute the command, wherein the processor has a register operable to store a parameter representative of a time duration, and wherein the processor is configured to send a signal to the memory system in response to a determination that the memory system fails to respond to the command within the time duration identified by the register; 
 receive, during execution of the command, the signal; and 
 abort, in response to the signal, the execution of the command. 
   
     
     
         11 . The memory system of  claim 10 , wherein the controller is further configured to, in response to the signal:
 identify a latency for retrieval of the data item; and   remap the memory address to store the data item for retrieval according to the latency identified in response to the signal.   
     
     
         12 . The memory system of  claim 11 , wherein the time duration identified by the register is shorter than a data retrieval latency of at least one of the plurality of memory components. 
     
     
         13 . The memory system of  claim 12 , wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof. 
     
     
         14 . The memory system of  claim 11 , wherein prior to the signal, the memory address is mapped to a first memory component, among the plurality of memory components, in the memory system to store the data item; and the controller is configured to identify the latency based on a time gap between the signal and the command and identify a second memory component, among the plurality of memory components, to store the data item for the memory address. 
     
     
         15 . The memory system of  claim 14 , wherein the processor is further configured to resend, after at least a predetermined period of time following the signal, the command to the memory system; and the controller is configured to relocate the data item from the first memory component to the second memory component with the predetermined period of time. 
     
     
         16 . The memory system of  claim 15 , wherein the processor is further configured to send, after sending the signal and before resending the command, a further command to retrieve data from an address different from the memory address; and the controller is configured to execute the further command in parallel with relocation of the data item from the first memory component to the second memory component. 
     
     
         17 . A system, comprising:
 a processor having:
 a register operable to store a parameter representative of a time duration; and 
 a plurality of execution units; and 
   a memory sub-system having:
 a plurality of memory components having different latencies in data retrieval; and 
 a controller coupled to the plurality of memory components; 
   wherein during execution of an instruction in the processor to load a data item from a memory address, the processor is configured to send a command to the memory sub-system;   wherein in response to a determination that the memory sub-system fails to respond to the command within the time duration identified by the register, the memory controller is configured to send a signal to the memory sub-system; and   wherein the controller is configured to, in response to the signal, abort execution of the command.   
     
     
         18 . The system of  claim 17 , wherein the plurality of memory components includes a first memory component having a first data retrieval latency and a second memory component having a second data retrieval latency shorter than the first data retrieval latency; and the controller is configured to relocate the data item for the memory address from the first memory component to the second memory component. 
     
     
         19 . The system of  claim 18 , wherein the controller is further configured to:
 identify a desired data retrieval latency for the data item based on a time gap between the command and the signal; and   select, based on the desired data retrieval latency for the data item, the second memory component, from the plurality of memory components to relocate the data item.   
     
     
         20 . The system of  claim 19 , wherein the plurality of memory components include dynamic random access memory, non-volatile random access memory, or flash memory, or any combination thereof.