Resistive memory cell

Abstract

Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.

What is claimed is: 
     
         1 . A resistive memory cell, comprising:
 a plurality of dielectric regions formed between a first electrode and a second electrode; and   a barrier dielectric region formed between each dielectric region of the plurality of dielectric regions; and   wherein the barrier dielectric region serves to reduce an oxygen diffusion rate associated with the plurality of dielectric regions.   
     
     
         2 . The resistive memory cell of  claim 1 , wherein the resistive memory cell is configured to have more than two non-volatile resistive states. 
     
     
         3 . The resistive memory cell of  claim 1 , wherein the plurality of dielectric regions is at least three dielectric regions. 
     
     
         4 . The resistive memory cell of  claim 1 , wherein the barrier dielectric region comprises silicon dioxide. 
     
     
         5 . The resistive memory cell of  claim 4 , wherein the barrier dielectric region has a thickness of 20 Angstroms or less. 
     
     
         6 . The resistive memory cell of  claim 1 , wherein the barrier dielectric region is a grain-boundary disruptor with respect to the plurality of dielectric regions. 
     
     
         7 . The resistive memory cell of  claim 1 , wherein the plurality of dielectric regions are amorphous regions, and wherein the barrier dielectric region is an amorphous region. 
     
     
         8 . The resistive memory cell of  claim 1 , wherein the plurality of dielectric regions are crystalline regions, and wherein the barrier dielectric region is an amorphous region. 
     
     
         9 . The resistive memory cell of  claim 1 , wherein the plurality of dielectric regions and the barrier dielectric region are horizontal laminates. 
     
     
         10 . A resistive memory cell, comprising:
 a first electrode;   a first dielectric region formed on the electrode;   a first barrier dielectric region formed on the first dielectric region, the first barrier dielectric region having a slower oxygen diffusion rate and/or being a grain-boundary disruptor relative to the first dielectric region;   a second dielectric region formed on the first barrier dielectric region; and   a second electrode formed on the second dielectric region.   
     
     
         11 . The resistive memory cell of  claim 10 , further comprising a second barrier dielectric region formed between the second dielectric region and a third dielectric region. 
     
     
         12 . The resistive memory cell of  claim 11 , wherein the first, second, and third dielectric regions each have a thickness of between 10 Angstroms and 100 Angstroms. 
     
     
         13 . The resistive memory cell of  claim 10 , wherein the first dielectric region, the second dielectric region, and the first barrier dielectric region are amorphous. 
     
     
         14 . The resistive memory cell of  claim 10 , further comprising a buffer dielectric region between the first electrode and the first dielectric region, the buffer dielectric region having a lower k value and higher resistance than the first dielectric region. 
     
     
         15 . The resistive memory cell of  claim 10 , wherein the first dielectric region is in contact with the first electrode and the second dielectric region is in contact with the second electrode. 
     
     
         16 . The resistive memory cell of  claim 10 , wherein the first barrier dielectric region comprises at least one of: silicon dioxide (SiO 2 ); aluminum oxide (Al 2 O 3 ); zirconium oxide (ZrO 2 ); and amorphous doped silicon. 
     
     
         17 . A resistive memory cell, comprising:
 a plurality of dielectric regions formed between a first electrode and a second electrode; and   a plurality of barrier dielectric regions, wherein each one of the plurality of barrier dielectric regions is formed between alternating instances of the plurality of dielectric regions; and   wherein the plurality of barrier dielectric region serve as a grain-boundary disruptors with respect to the plurality of dielectric regions.   
     
     
         18 . The resistive memory cell of  claim 17 , wherein the plurality of dielectric regions include a metal oxide material. 
     
     
         19 . The resistive memory cell of  claim 17 , wherein one of the plurality of dielectric regions is formed on the first electrode, and wherein the second electrode is formed on a different one of the plurality of dielectric regions. 
     
     
         20 . The resistive memory cell of  claim 17 , wherein the thickness of the resistive memory cell materials excluding the first electrode and the second electrode is less than 1000 Angstroms.