System, method and apparatus for race-condition true random number generator

Abstract

The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

1 . A system on chip (SOC) to generate substantially uniform, nondeterministic data stream, comprising:
 a first variable delay chain (VDC) circuitry having a first delay chain and a second delay chain, each of the first and the second delay chains further comprising a respective register array and an adder array, the first VDC circuitry to provide a first race output bit and a second race output bit;   a race condition latch circuitry to select a race output winner from the first and the second race output bits; and   a bit logic circuitry to receive the selected race output winner bit and provide an output bit corresponding to the selected race output;   a register to receive and store output bits corresponding a plurality of selected race outputs, the register to provide an output bit stream periodically;   a concatenator to interleave different output bit streams to provide a partially entropic output bit corresponding to a plurality of selected race outputs; and   an entropy extraction circuitry to convert the partially entropic output bit signal into a substantially uniform, nondeterministic data stream.   
     
     
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