Semiconductor memory device

Abstract

A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, first and second pillars, and a first member. The first conductive layer includes a first portion, a second portion, and a third portion above the second portion. The second conductive layers are stacked above the first conductive layer. The first pillar includes a first semiconductor layer in contact with the first portion in a direction crossing the stacked direction. The second pillar is provided to penetrate the second conductive layers and the third portion in the stacked direction. The first member is provided between the first and second pillars and between the second and third portions.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a plurality of first conductive layers stacked above a substrate and spaced apart from each other in a first direction intersecting a surface of the substrate, each of the first conductive layers extending in a second direction intersecting the first direction;   a second conductive layer extending in the second direction above the first conductive layers;   a third conductive layer extending in the second direction above the first conductive layers, the third conductive layer being arranged adjacently to the second conductive layer in a third direction intersecting both the first direction and the second direction;   a plurality of first pillars extending through the first conductive layers and the second conductive layer in the first direction, intersections of the first pillars with at least one of the first conductive layers functioning as first memory cells and intersections of the first pillars with the second conductive layer functioning as first select transistors;   a plurality of second pillars extending through the first conductive layers and the third conductive layer in the first direction, intersections of the second pillars with at least one of the first conductive layers functioning as second memory cells and intersections of the second pillars with the third conductive layer functioning as second select transistors;   a plurality of third pillars extending through the first conductive layers and extending between the second conductive layer and the third conductive layer in the first direction;   a first insulator provided in a first slit extending in the first and second directions along one side of the first conductive layers in the third direction, the first insulator continuously covering bottom and both side surfaces extending in the second direction of the first slit;   a second insulator provided in a second slit extending in the first and second directions along the other side of the first conductive layers in the third direction, the second insulator continuously covering bottom and both side surfaces extending in the second direction of the second slit; and   a third insulator provided in a third slit extending in the first and third directions, one end of the third slit in the third direction being coupled to one end of the first slit in the second direction and the other end of the third slit in the third direction being coupled to one end of the second slit in the second direction, and the third insulator being in contact with ends of the first conductive layers in the second direction.   
     
     
         2 . The device according to  claim 1 , further comprising:
 a source layer provided between the substrate and the first conductive layers, lower ends of the first and second pillars reaching the source layer, wherein   a first portion of the source layer is exposed to the bottom surface of the first slit and a second portion of the source layer is exposed to the bottom surface of the second slit, and   the first insulator covers the exposed first portion of the source layer wholly and the second insulator covers the exposed second portion of the source layer wholly.   
     
     
         3 . The device according to  claim 1 , further comprising:
 an insulating member provided between the second conductive layer and the third conductive layer.   
     
     
         4 . The device according to  claim 3 , wherein
 an upper end of the insulating member and upper ends of the third pillars are aligned in the first direction.   
     
     
         5 . The device according to  claim 3 , wherein
 portions of the insulating member and the third pillars are alternately arranged in the second direction between the second conductive layer and the third conductive layer.   
     
     
         6 . The device according to  claim 5 , wherein
 a diameter of each of the third pillars is greater than a width of the insulating member in the third direction in a cross section including the second and third conductive layers.   
     
     
         7 . The device according to  claim 1 , further comprising:
 a plurality of fourth conductive layers stacked apart from the first conductive layers in the second direction above the substrate and spaced apart from each other in the first direction, each of the fourth conductive layers extending in the second direction;   a fifth conductive layer extending in the second direction above the fourth conductive layers;   a sixth conductive layer extending in the second direction above the fourth conductive layers, the sixth conductive layer being arranged adjacently to the fifth conductive layer in the third direction;   a plurality of fourth pillars extending through the fourth conductive layers and the fifth conductive layer in the first direction, intersections of the fourth pillars with at least one of the fourth conductive layers functioning as third memory cells and intersections of the fourth pillars with the fifth conductive layer functioning as third select transistors;   a plurality of fifth pillars extending through the fourth conductive layers and the sixth conductive layer in the first direction, intersections of the fifth pillars with at least one of the fourth conductive layers functioning as fourth memory cells and intersections of the fifth pillars with the sixth conductive layer functioning as fourth select transistors;   a plurality of sixth pillars extending through the fourth conductive layers and extending between the fifth conductive layer and the sixth conductive layer in the first direction;   a fourth insulator provided in a fourth slit extending in the first and second directions along one side of the fourth conductive layers in the third direction, the fourth insulator continuously covering bottom and both side surfaces extending in the second direction of the fourth slit;   a fifth insulator provided in a fifth slit extending in the first and second directions along the other side of the fourth conductive layers in the third direction, the fifth insulator continuously covering bottom and both side surfaces extending in the second direction of the fifth slit; and   a sixth insulator provided in a sixth slit extending in the first and third directions, one end of the sixth slit in the third direction being coupled to one end of the fourth slit in the second direction and the other end of the sixth slit in the third direction being coupled to one end of the fifth slit in the second direction, and the sixth insulator being in contact with ends of the fourth conductive layers in the second direction.   
     
     
         8 . The device according to  claim 7 , wherein
 the ends of the fourth conductive layers face the ends of the first conductive layers in the second direction with the third and sixth insulators interposed therebetween.   
     
     
         9 . The device according to  claim 8 , further comprising:
 inter-area conductive layers disposed between the third insulator and the sixth insulator above the substrate and spaced apart from each other in the first direction.   
     
     
         10 . The device according to  claim 9 , further comprising:
 a plurality of seventh pillars extending through the inter-area conductive layers in the first direction.   
     
     
         11 . The device according to  claim 7 , wherein
 the first and second memory cells and the first and second select transistors belong to a first memory plane, and the third and fourth memory cells and the third and fourth select transistors belong to a second memory plane different from the first memory plane.   
     
     
         12 . The device according to  claim 1 , further comprising:
 a seventh conductive layer extending in the second direction above the second conductive layer, the first pillars extending through the seventh conductive layer in the first direction, and   an eighth conductive layer extending in the second direction above the third conductive layer and being arranged adjacently to the seventh conductive layer in the third direction, the second pillars extending through the eighth conductive layer in the first direction, wherein   the third pillars extend between the seventh conductive layer and the eighth conductive layer in the first direction.   
     
     
         13 . The device according to  claim 12 , further comprising:
 an insulating member provided between the second conductive layer and the third conductive layer and between the seventh conductive layer and the eighth conductive layer.   
     
     
         14 . A semiconductor memory device comprising:
 a substrate including a first block area;   a stacked structure of conductive layers provided above the substrate; and   a separation member provided in a slit extending inside the stacked structure, the first block area being partitioned by the slit above the substrate, wherein   the stacked structure includes:   a plurality of first conductive layers stacked separately in a first direction intersecting a surface of the substrate and disposed correspondingly to the first block area, each of the first conductive layers extending in a second direction intersecting the first direction;   a second conductive layer extending in the second direction above the first conductive layers;   a third conductive layer extending in the second direction above the first conductive layers, the third conductive layer being arranged adjacently to the second conductive layer in a third direction intersecting both the first direction and the second direction;   a plurality of first pillars extending through the first conductive layers and the second conductive layer in the first direction, intersections of the first pillars with at least one of the first conductive layers functioning as first memory cells and intersections of the first pillars with the second conductive layer functioning as first select transistors;   a plurality of second pillars extending through the first conductive layers and the third conductive layer in the first direction, intersections of the second pillars with at least one of the first conductive layers functioning as second memory cells and intersections of the second pillars with the third conductive layer functioning as second select transistors; and   a plurality of third pillars extending through the first conductive layers and extending between the second conductive layer and the third conductive layer in the first direction,   the slit includes first and second parts both extending in the first and second directions and a third part extending in the first and third directions between respective ends of the first and second parts of the slit, the first block area above the substrate being sandwiched by the first and second parts of the slit in the third direction, and   the separation member contacts with ends of the first conductive layers in the second direction and includes an insulator covering an inner surface of the slit continuously in the first to third parts of the slit.   
     
     
         15 . The device according to  claim 14 , wherein
 the substrate further includes a second block area adjacent to the first block area in the third direction, the second block area being partitioned by the slit above the substrate,   the slit further includes a fourth part extending in the first and second directions, the second block area above the substrate being sandwiched by the second and fourth parts of the slit in the third direction and the third part of the slit further extending between respective ends of the second and fourth parts of the slit, and   a portion of the conductive layers other than the first conductive layers in the stacked structure contacts with the separation member in the third part of the slit at its end in the second direction, the portion of the conductive layers extending in the second direction within the second block area.   
     
     
         16 . The device according to  claim 14 , further comprising:
 a source layer provided between the substrate and the first conductive layers, lower ends of the first and second pillars reaching the source layer, wherein   a first portion of the source layer is exposed to a bottom surface of the first part of the slit and a second portion of the source layer is exposed to a bottom surface of the second part of the slit, and   the insulator included in the separation member covers the exposed first and second portions of the source layer wholly.   
     
     
         17 . The device according to  claim 14 , further comprising:
 an insulating member provided between the second conductive layer and the third conductive layer.   
     
     
         18 . The device according to  claim 17 , wherein
 an upper end of the insulating member and upper ends of the third pillars are aligned in the first direction.   
     
     
         19 . The device according to  claim 17 , wherein
 portions of the insulating member and the third pillars are alternately arranged in the second direction between the second conductive layer and the third conductive layer.   
     
     
         20 . The device according to  claim 19 , wherein
 a diameter of each of the third pillars is greater than a width of the insulating member in the third direction in a cross section including the second and third conductive layers.