Deposition of graphene on a dielectric surface for next generation interconnects

Abstract

An integrated circuit structure, comprises a dielectric material having an opening therein, the opening defined by sides and a bottom. A graphene barrier material is conformal to the sides and the bottom of the opening, and a conductive metal over the graphene barrier material that fills at least a portion of a remainder of the opening in the dielectric material. The graphene barrier is formed by applying a non-hydrogen based plasma pretreatment to the dielectric surface, including the sides and the bottom of the opening, to substantially remove any passivation and provide an activated dielectric surface. A carbon-based precursor is exposed to the activated dielectric surface at less than approximately 400° C. to form the graphene barrier.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a dielectric material having an opening therein, the opening having sides;   a graphene barrier material conformal to the sides of the opening; and   a conductive metal adjacent to the graphene barrier material and filling a remainder of the opening in the dielectric material, the conductive metal in direct contact with the graphene barrier material.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the graphene barrier material is directly on the dielectric material. 
     
     
         3 . The integrated circuit structure of  claim 1 , wherein the graphene barrier material is less than approximately 5 Angstroms in thickness. 
     
     
         4 . The integrated circuit structure of  claim 1 , wherein the conductive metal and the graphene barrier material comprise a conductive structure. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the dielectric material comprise an oxide-based material having characteristics of a low-k material. 
     
     
         6 . An integrated circuit structure, comprising:
 a conductive metal structure;   a graphene barrier material completely laterally surrounding the conductive metal structure, wherein the conductive metal is in direct contact with the graphene barrier material; and   a dielectric material completely laterally surrounding the graphene barrier material.   
     
     
         7 . The integrated circuit structure of  claim 6 , wherein the dielectric material is in direct contact with the graphene barrier material. 
     
     
         8 . The integrated circuit structure of  claim 6 , wherein the graphene barrier material is less than approximately 5 Angstroms in thickness. 
     
     
         9 . The integrated circuit structure of  claim 6 , wherein the conductive metal and the graphene barrier material comprise a conductive structure. 
     
     
         10 . The integrated circuit structure of  claim 6 , wherein the dielectric material comprise an oxide-based material having characteristics of a low-k material. 
     
     
         11 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a dielectric material having an opening therein, the opening having sides; 
 a graphene barrier material conformal to the sides of the opening; and 
 a conductive metal adjacent to the graphene barrier material and filling a remainder of the opening in the dielectric material, the conductive metal in direct contact with the graphene barrier material. 
   
     
     
         12 . The computing device of  claim 11 , further comprising:
 a memory coupled to the board.   
     
     
         13 . The computing device of  claim 11 , further comprising:
 a communication chip coupled to the board.   
     
     
         14 . The computing device of  claim 11 , further comprising:
 a camera coupled to the board.   
     
     
         15 . The computing device of  claim 11 , wherein the component is a packaged integrated circuit die. 
     
     
         16 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
 conductive metal structure; 
 graphene barrier material completely laterally surrounding the conductive metal structure, wherein the conductive metal is in direct contact with the graphene barrier material; and 
 a dielectric material completely laterally surrounding the graphene barrier material. 
   
     
     
         17 . The computing device of  claim 16 , further comprising:
 a memory coupled to the board.   
     
     
         18 . The computing device of  claim 16 , further comprising:
 a communication chip coupled to the board.   
     
     
         19 . The computing device of  claim 16 , further comprising:
 a camera coupled to the board.   
     
     
         20 . The computing device of  claim 16 , wherein the component is a packaged integrated circuit die.