System and method for cleaning contact elements and support hardware using functionalized surface microfeatures

Abstract

A cleaning material, device, and method for predictably cleaning the contact elements and support hardware of a tester interface, such as a probe card and a test socket, in which the cleaning pad has a predetermined configuration appropriate for the particular pin contact elements and a substrate having a defined functionalized surface topology and geometry which can be introduced into the testing apparatus during the normal testing operations. The cleaning material has a predetermined topography with a plurality of functional 3-dimensional (3D) microstructures that provide performance characteristics which are not possible with a non-functionalized and flat surface.

What is claimed is: 
     
         1 . A method for cleaning contact elements and support structures of a testing interface used for wafer level or package level IC semiconductor device testing, the method comprising:
 performing a testing operation of the wafer level or package level IC semiconductor devices; and   performing a cleaning operation using a cleaning device that has a cleaning media having a plurality of functionalized microfeatures that each have a body with a width a height, a spacing between each body and dimensional properties that optimize the cleaning media so that the contact area and surrounding support hardware are cleaned without modification or damage, each microfeature extending away from a top surface of the cleaning media and the cleaning media having a plurality of abrasive particles having a Mohs Hardness of 7 or greater uniformly distributed within the body of each microfeature, a cleaning layer applied across the top surface of the cleaning media having predetermined characteristics that clean contaminants from the pin contact elements and support hardware and one or more intermediate rigid or compliant underlayers underneath the cleaning media, wherein each underlayer has a modulus of elasticity range between more than 40-MPa to 600-MPa, each layer has a thickness between 25-um and 300-um and each layer has a hardness between 30 Shore A and 90 Shore A.   
     
     
         2 . The method of  claim 1 , wherein performing a cleaning operation using a cleaning device further comprises using a polymer layer that is 10 to 100 um thick that has a predetermined specific gravity, elasticity, tackiness, planarity, thickness and porosity. 
     
     
         3 . The method of  claim 1 , wherein performing a cleaning operation using a cleaning device further comprises using a plurality of positive microfeatures that extends upwards away from the top surface of the cleaning media. 
     
     
         4 . The method of  claim 1 , wherein performing a cleaning operation using a cleaning device further comprises using a plurality of negative microfeature that extends downwards away from the top surface of the cleaning media. 
     
     
         5 . A method for cleaning pin contact elements and support hardware in a semiconductor testing apparatus, the method comprising:
 performing testing of a device under test having a predetermined configuration of one of solder balls, pillars, copper-pillar bumps, and gold bumps; and   performing cleaning of the pin contact elements and support hardware using a cleaning device having a cleaning media with a plurality of geometrical surface features that emulate wherein the cleaning balls and cleaning pillars are further comprised of a plurality of abrasive particles distributed within the features and having a Mohs Hardness of 7 or greater for cleaning contact elements and support structures of testing interfaces, a cleaning layer applied across a top surface of each geometric surface feature and along a side of each geometric surface feature having predetermined characteristics that clean contaminants from the pin contact elements and support hardware and a substrate onto which the cleaning media is attached, having a configuration suitable to be introduced into the testing apparatus during normal testing operating of the testing apparatus, wherein the substrate comprises a surrogate semiconductor wafer or packaged IC device.