Read refresh operation

Abstract

Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device).

1 . (canceled) 
     
     
         2 . A method, comprising:
 applying a first voltage to a memory cell of a sub-block of a memory array as part of a read refresh operation for the sub-block;   reading a logic state of the memory cell based at least in part on applying the first voltage, wherein reading the logic state of the memory cell comprises detecting whether a first snapback event associated with the memory cell occurs; and   applying, to the memory cell, one or more additional voltages as part of the read refresh operation based at least in part on detecting whether the first snapback event occurs.   
     
     
         3 . The method of  claim 2 , wherein applying the one or more additional voltages as part of the read refresh operation comprises:
 applying, to the memory cell, a second voltage based at least in part on detecting that the first snapback event has not occurred; and   detecting whether a second snapback event associated with the memory cell occurs in response to applying the second voltage.   
     
     
         4 . The method of  claim 3 , further comprising:
 applying, to the memory cell, a third voltage based at least in part on detecting that the second snapback event has occurred, wherein the third voltage reprograms the logic state of the memory cell as part of the read refresh operation.   
     
     
         5 . The method of  claim 4 , wherein the second voltage and the third voltage are applied based at least in part on determining that a quantity of read refresh operations performed on the sub-block is less than a first threshold and greater than a second threshold. 
     
     
         6 . The method of  claim 3 , wherein the read refresh operation is a first type read refresh operation. 
     
     
         7 . The method of  claim 2 , wherein applying the one or more additional voltages as part of the read refresh operation comprises:
 applying, to the memory cell, a fourth voltage based at least in part on detecting that the first snapback event has not occurred, wherein a polarity of the fourth voltage is different than a polarity of the first voltage; and   detecting whether a third snapback event associated with the memory cell occurs in response to applying the fourth voltage.   
     
     
         8 . The method of  claim 7 , further comprising:
 applying, to the memory cell, a fifth voltage based at least in part on detecting that the third snapback event has occurred, wherein a polarity of the fifth voltage is different from the polarity of the fourth voltage, and wherein the fifth voltage programs the memory cell to a second logic state as part of the read refresh operation.   
     
     
         9 . The method of  claim 8 , further comprising:
 applying, to the memory cell, a sixth voltage based at least in part on applying the fifth voltage, wherein the sixth voltage reprograms the logic state to the memory cell as part of the read refresh operation.   
     
     
         10 . The method of  claim 9 , wherein the fourth voltage, the fifth voltage, and the sixth voltage are applied based at least in part on determining that a quantity of read refresh operations performed on the sub-block is less than a second threshold. 
     
     
         11 . The method of  claim 7 , wherein the read refresh operation is a second type of read refresh operation. 
     
     
         12 . The method of  claim 2 , wherein applying the one or more additional voltages as part of the read refresh operation comprises:
 applying, to the memory cell, a seventh voltage based at least in part on detecting that the first snapback event has occurred, wherein the seventh voltage reprograms the logic state of the memory cell as part of the read refresh operation.   
     
     
         13 . The method of  claim 2 , further comprising:
 initiating the read refresh operation based at least in part on a quantity of access operations performed on the sub-block.   
     
     
         14 . The method of  claim 2 , further comprising:
 receiving, from a host device, a first operation code to perform a first type of read refresh operation based at least in part on a first quantity of write operations performed on the sub-block over a first duration of time satisfying a first threshold; and   receiving, from the host device, a second operation code to perform a second type of read refresh operation based at least in part on a second quantity of write operations performed on the sub-block over a second duration of time satisfying a second threshold less than the first threshold.   
     
     
         15 . The method of  claim 2 , further comprising:
 incrementing a counter based at least in part on an access operation being performed on the sub-block, wherein the read refresh operation is performed based at least in part on a value of the counter.   
     
     
         16 . An apparatus, comprising:
 a memory array; and   a controller coupled with the memory array, wherein the controller is configured to cause the apparatus to:
 apply a first voltage to a memory cell of a sub-block of the memory array as part of a read refresh operation for the sub-block; 
 read a logic state of the memory cell based at least in part on applying the first voltage, wherein reading the logic state of the memory cell comprises detecting whether a first snapback event associated with the memory cell occurs; and 
 apply, to the memory cell, one or more additional voltages as part of the read refresh operation based at least in part on detecting whether the first snapback event occurs. 
   
     
     
         17 . The apparatus of  claim 16 , wherein the controller is configured to apply the one or more additional voltages by causing the apparatus to:
 apply, to the memory cell, a second voltage based at least in part on detecting that the first snapback event has not occurred; and   apply, to the memory cell, a third voltage based at least in part on detecting that a second snapback event associated with the memory cell has occurred in response to applying the second voltage, wherein the third voltage reprograms the logic state of the memory cell as part of the read refresh operation.   
     
     
         18 . The apparatus of  claim 16 , wherein the controller is configured to apply the one or more additional voltages by causing the apparatus to:
 apply, to the memory cell, a fourth voltage based at least in part on detecting that the first snapback event has not occurred, wherein a polarity of the fourth voltage is different than a polarity of the first voltage;   apply, to the memory cell, a fifth voltage based at least in part on detecting that a third snapback event associated with the memory cell has occurred, wherein a polarity of the fifth voltage is different from the polarity of the fourth voltage, and wherein the fifth voltage programs the memory cell to a second logic state as part of the read refresh operation; and   apply, to the memory cell, a sixth voltage based at least in part on applying the fifth voltage, wherein the sixth voltage reprograms the logic state to the memory cell as part of the read refresh operation.   
     
     
         19 . The apparatus of  claim 16 , wherein the controller is configured to apply the one or more additional voltages by causing the apparatus to:
 apply, to the memory cell, a seventh voltage based at least in part on detecting that the first snapback event has occurred, wherein the seventh voltage reprograms the logic state of the memory cell as part of the read refresh operation.   
     
     
         20 . The apparatus of  claim 16 , wherein the controller is configured to apply the one or more additional voltages by causing the apparatus to:
 initiate the read refresh operation based at least in part on a quantity of access operations performed on the sub-block.   
     
     
         21 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
 apply a first voltage to a memory cell of a sub-block of a memory array of the electronic device as part of a read refresh operation for the sub-block;   read a logic state of the memory cell based at least in part on applying the first voltage, wherein reading the logic state of the memory cell comprises detecting whether a first snapback event associated with the memory cell occurs; and   apply, to the memory cell, one or more additional voltages as part of the read refresh operation based at least in part on detecting whether the first snapback event occurs.