Fuse array structure

Abstract

The present disclosure provides a semiconductor structure with a fuse array structure having a buried word line disposed within a substrate. The semiconductor structure includes a substrate having a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a first gate structure disposed over the first doped region and electrically connected to a first bit line; a second gate structure to disposed over the first surface of the substrate and electrically connected to a second bit line; and a buried word line disposed within the first recess and disposed between the first gate structure and the second gate structure. The second gate structure is at least partially disposed within the second recess of the substrate.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, a first recess indented into the substrate and disposed between the first doped region and the second doped region, and a second recess indented into the substrate and adjacent to the second doped region;   a first gate structure disposed over the first doped region and electrically connected to a first bit line;   a second gate structure disposed over the first surface of the substrate and electrically connected to a second bit line; and   a buried word line disposed within the first recess and disposed between the first gate structure and the second gate structure,   wherein the second gate structure is at least partially disposed within the second recess of the substrate.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein a depth of the second recess is substantially less than a depth of the first recess. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the second gate structure includes a gate dielectric disposed within the second recess of the substrate. 
     
     
         4 . The semiconductor structure of  claim 3 , wherein the gate dielectric is breakable upon a voltage bias between the buried word line and the second bit line. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein the voltage bias between the buried word line and the second bit line is substantially greater than 2V. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the buried word line is disposed under and away from the first surface of the substrate. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein the buried word line is disposed under and away from the first doped region and the second doped region. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the recess extends from the first surface of substrate towards a second surface of the substrate opposite to the first surface. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the second gate structure includes a fuse dielectric disposed on the second doped region. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein the fuse dielectric is breakable when a voltage bias between the buried word line and the fuse bit line is substantially greater than 5V. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein the buried word line is disposed under and away from the fuse dielectric. 
     
     
         12 . The semiconductor structure of  claim 9 , wherein the fuse dielectric includes oxide or metal contained oxide 
     
     
         13 . The semiconductor structure of  claim 1 , wherein the first doped region and the second doped region are of a same conductive type. 
     
     
         14 . The semiconductor structure of  claim 1 , wherein the buried word line includes a conductor and an isolation layer disposed within the recess and between the substrate and the conductor. 
     
     
         15 . The semiconductor structure of  claim 14 , wherein the isolation layer is disposed conformal to a sidewall of the recess. 
     
     
         16 . The semiconductor structure of  claim 14 , wherein the isolation layer includes a first portion disposed between the conductor and the substrate, and a second portion disposed under the conductor, and wherein a thickness of the first portion is substantially greater than a thickness of the second portion. 
     
     
         14 . The semiconductor structure of  claim 14 , wherein the isolation layer includes high-k (high dielectric constant) dielectric material. 
     
     
         18 . The semiconductor structure of  claim 1 , wherein the control bit line and the fuse bit line are substantially orthogonal to the buried word line. 
     
     
         19 . The semiconductor structure of  claim 1 , wherein the control bit line and the fuse bit line are substantially parallel to each other.