Methods and apparatus for testing isfet arrays

Abstract

The invention provides testing of a chemically-sensitive transistor device, such as an ISFET device, without exposing the device to liquids. In one embodiment, the invention performs a first test to calculate a resistance of the transistor. Based on the resistance, the invention performs a second test to transition the testing transistor among a plurality of modes. Based on corresponding measurements, a floating gate voltage is then calculated with little or no circuitry overhead. In another embodiment, the parasitic capacitance of at least either the source or drain is used to bias the floating gate of an ISFET. A driving voltage and biasing current are applied to exploit the parasitic capacitance to test the functionality of the transistor.

What is claimed is: 
     
         1 . A device, comprising:
 an array of chemical detection elements, each element including:
 a chemically-sensitive field effect transistor having a semiconductor body terminal, a source terminal, a drain terminal, and a floating gate terminal; and 
   a testing circuit including:
 a plurality of driving voltage terminals at each side of the array, the plurality of driving voltage terminals coupled to a plurality of source terminals and a plurality of body terminals; 
 a current source coupled to the drain terminal of at least one element in the array to measure a drain current by converting the drain current into corresponding voltage measurements. 
   
     
     
         2 . The device of  claim 1 , wherein the chemically-sensitive transistor is an ISFET. 
     
     
         3 . The device of  claim 1 , wherein the testing circuit is configured to drive the chemically-sensitive field effect transistors to operate in different modes. 
     
     
         4 . The device of  claim 3 , wherein the different modes include triode mode and saturation mode. 
     
     
         5 . A device, comprising:
 an array of detection elements, each element including:
 a field effect transistor having a floating gate, a first terminal, a second terminal, and an overlap capacitance between the floating gate and at least one of the first and second terminals; and 
   a testing circuit including:
 a driving voltage terminal coupled to at least one first terminal, 
 a biasing current terminal coupled to at least one second terminal, and 
 an output voltage measurement terminal coupled to the at least one second terminal. 
   
     
     
         6 . The device of  claim 5 , wherein each field effect transistor is an ISFET. 
     
     
         7 . The device of  claim 5 , wherein the first terminal of each field effect transistor is a drain terminal and the second terminal of each field effect transistor is a source terminal. 
     
     
         8 . The device of  claim 5 , wherein the overlap capacitance is formed by a gate oxide layer material that partially overlaps a terminal implant of the transistor.