Systems, methods and apparatus for low latency memory integrity mac for trust domain extensions

Abstract

The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment, the disclosure relates to a computing device (e.g., a memory protection engine) to protect integrity of one or more memory circuitry. The computing device may include: a key-hash operator configured to provide a Message Authentication Code (MAC) for a secure Hash Algorithm (SHA) as a function of a hash-key, MAC-key, metadata and data; a multi-round (MR) circuitry configured to receive the MAC from the key-hash operator and to compute substantially all SHA round-functions during each clock cycle, the multi-round circuitry further comprising combination logic to process all sub-round functions of the SHA function substantially simultaneously; and a Memory Integrity Pipeline (MIP) engine to compute a hash digest, the hash digest further comprising a MAC key, a metadata and the cache line data; the MIP further comprising an input prep logic, an SHA pipeline logic and an MAC validation logic.

What is claimed is: 
     
         1 . At least one machine-readable medium comprising instructions that, when executed by computing hardware, including a processor circuitry coupled to a memory circuitry, cause the computing hardware to authenticate instruction on the memory circuitry by:
 performing a write operation, the write operation including:
 forming an SHA input block on a cache-line data, the input block formed as a function of a Message Authentication Code (MAC) key, a memory address and other metadata and the cache-line data; 
 directing the SHA input block into a data pipeline to form a first SHA digest; 
 truncating the first SHA digest to a first length to form a first MAC input (X); and 
 writing the first MAC input with the cache-line data into one or more memory blocks; 
   performing a read operation, the read operation including:
 obtaining the MAC key, the memory address and the at least one metadata; 
 forming a second SHA input block on a read cache-line data as a function of the MAC key, the memory address, the at least one metadata and the cache-line that just read out from memory; 
 directing the second SHA input block into the SHA pipeline to form a second SHA digest; 
 truncate the second SHA digest to a second length to form a second MAC (Y); and 
 compare the second MAC (Y) and first MAC (X) that is read out from memory with cache-line data. 
   
     
     
         2 . The machine-readable medium of  claim 1 , wherein the data pipeline communicates data between the circuitry and the processing circuitry. 
     
     
         3 . The machine-readable medium of  claim 1 , wherein the first length is one of 32, 64 or 128 bits. 
     
     
         4 . The machine-readable medium of  claim 1 , wherein performing the write operation further comprises obtaining the cache-line data and the first MAC input (X) from the memory. 
     
     
         5 . The machine-readable medium of  claim 1 , wherein performing the write operation further comprises obtaining the MAC key, the memory address and the at least one metadata from one or more internal registers of a memory integrity engine. 
     
     
         6 . The machine-readable medium of  claim 1 , further comprising authenticating memory integrity by comparing the first MAC input with the second MAC input (Y). 
     
     
         7 . The machine-readable medium of  claim 6 , further comprising validating memory integrity if the first MAC input (or X) and the second MAC input (or Y) are identical. 
     
     
         8 . The machine-readable medium of  claim 1 , wherein the instructions are executed on a hardware, software or a combination of hardware and software. 
     
     
         9 . A method to authenticate instructions to a memory circuitry to verify memory integrity, the method comprising:
 performing a write operation, the write operation including:
 forming an SHA input block on a cache-line data, the input block formed as a function of a Message Authentication Code (MAC) key, a memory address and other metadata and the cache-line data; 
 directing the SHA input block into a data pipeline to form a first SHA digest; 
 truncating the first SHA digest to a first length to form a first MAC input (X); and 
 writing the first MAC input with the cache-line data into one or more memory blocks; 
   performing a read operation, the read operation including:
 obtaining the MAC key, the memory address and the at least one metadata; 
 forming a second SHA input block on a read cache-line data as a function of the MAC key, the memory address, the at least one metadata and the cache-line that just read out from memory; 
 directing the second SHA input block into the SHA pipeline to form a second SHA digest; 
 truncate the second SHA digest to a second length to form a second MAC (Y); and 
 compare the second MAC (Y) and first MAC (X) that is read out from memory with cache-line data. 
   
     
     
         10 . The method of  claim 9 , wherein the data pipeline communicates data between the circuitry and the processing circuitry. 
     
     
         11 . The method of  claim 9 , wherein the first length is one of 32, 64 or 128 bits. 
     
     
         12 . The method of  claim 9 , wherein performing the write operation further comprises obtaining the cache-line data and the first MAC input (X) from the memory. 
     
     
         13 . The method of  claim 9 , wherein performing the write operation further comprises obtaining the MAC key, the memory address and the at least one metadata from one or more internal registers of a memory integrity engine. 
     
     
         14 . The method of  claim 9 , further comprising authenticating memory integrity by comparing the first MAC input with the second MAC input. 
     
     
         15 . The method of claim  24 , further comprising validating memory integrity if the first MAC input and the second MAC input are identical. 
     
     
         16 . The method of claim  20 , wherein the instructions are executed on a hardware, software or a combination of hardware and software.