US2022059531A1PendingUtilityA1

Semiconductor device

Assignee: SEMICONDUCTOR ENERGY LABPriority: Oct 30, 2009Filed: Nov 8, 2021Published: Feb 24, 2022
Est. expiryOct 30, 2029(~3.3 yrs left)· nominal 20-yr term from priority
H10D 86/423G11C 11/404H10D 86/60H10D 89/10H10D 84/83G11C 16/02G11C 11/405H01L 27/1225H01L 27/1052H01L 27/115H01L 27/088H01L 27/0207H01L 27/1156H01L 27/11517H10B 41/70H10B 41/00H10B 69/00
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Claims

Abstract

It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first transistor comprising silicon in a channel formation region; and   a second transistor comprising an oxide semiconductor layer in a channel formation region,   wherein a first insulating layer is over the gate electrode of the first transistor,   wherein a first conductive layer is over the first insulating layer and electrically connected to one of a source and a drain of the second transistor,   wherein the oxide semiconductor layer is over the first insulating layer and in contact with a top surface of the first conductive layer,   wherein a second insulating layer is over the oxide semiconductor layer,   wherein a second conductive layer is over the second insulating layer and electrically connected to the first conductive layer through a first opening of the second insulating layer,   wherein the second conductive layer is electrically connected to the gate electrode of the first transistor through an opening of the first insulating layer and a second opening of the second insulating layer, and   wherein a third conductive layer is over the second insulating layer and electrically connected to one of a source and a drain of the first transistor.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein the silicon is a single crystal silicon. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein the oxide semiconductor layer and the second opening of the second insulating layer do not overlap each other. 
     
     
         5 . The semiconductor device according to  claim 2 , further comprising a capacitor electrically connected to a gate electrode of the first transistor.

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