Designs and methods for conductive bumps

Abstract

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

What is claimed is: 
     
         1 . An assembly comprising:
 a die;   a pad on the die, the pad including aluminum;   a passivation layer on the die, the passivation layer having an opening over the pad;   a base layer metal on the pad in the opening of the passivation layer, the base layer metal further on a portion of the passivation layer, and the base layer metal including titanium;   a copper bump on the base layer metal;   a diffusion barrier layer on the copper bump, the diffusion barrier layer including nickel;   a conductive material above the diffusion barrier layer, the conductive material comprising tin and copper; and   a solder layer on the conductive material, the solder layer comprising tin, silver and copper.   
     
     
         2 . The assembly of  claim 1 , wherein the diffusion barrier layer has a thickness of approximately 5 microns. 
     
     
         3 . The assembly of  claim 1 , wherein the passivation layer comprises silicon and nitrogen. 
     
     
         4 . The assembly of  claim 1 , wherein the passivation layer comprises a polyimide. 
     
     
         5 . The assembly of  claim 1 , wherein the base layer metal further comprises copper. 
     
     
         6 . The assembly of  claim 1 , wherein the conductive material further comprises silver. 
     
     
         7 . The assembly of  claim 1 , wherein the conductive material further comprises antimony. 
     
     
         8 . The assembly of  claim 1 , wherein the conductive material further comprises bismuth. 
     
     
         9 . An assembly comprising:
 a die;   a pad on the die, the pad including aluminum;   a passivation layer on the die, the passivation layer having an opening over the pad;   a first layer on the pad in the opening of the passivation layer, the first layer further on a portion of the passivation layer, and the first layer including titanium;   a copper bump on the first layer;   a second layer on the copper bump, the second layer including nickel;   a conductive material above the second layer, the conductive material comprising copper; and   a solder layer on the conductive material, the solder layer comprising tin, silver and copper.   
     
     
         10 . The assembly of  claim 9 , wherein the conductive material further comprises tin. 
     
     
         11 . The assembly of  claim 9 , wherein the second layer has a thickness of approximately 5 microns. 
     
     
         12 . The assembly of  claim 9 , wherein the first layer is a base metal layer. 
     
     
         13 . The assembly of  claim 9 , wherein the second layer is a diffusion barrier layer. 
     
     
         14 . The assembly of  claim 9 , wherein the passivation layer comprises silicon and nitrogen. 
     
     
         15 . The assembly of  claim 9 , wherein the passivation layer comprises a polyimide. 
     
     
         16 . A system, comprising:
 a circuit board; and   an assembly coupled to the circuit board, the assembly comprising:
 a die; 
 a pad on the die, the pad including aluminum; 
 a passivation layer on the die, the passivation layer having an opening over the pad; 
 a base layer metal on the pad in the opening of the passivation layer, the base layer metal further on a portion of the passivation layer, and the base layer metal including titanium; 
 a copper bump on the base layer metal; 
 a diffusion barrier layer on the copper bump, the diffusion barrier layer including nickel; 
 a conductive material above the diffusion barrier layer, the conductive material comprising tin and copper; and 
 a solder layer on the conductive material, the solder layer comprising tin, silver and copper. 
   
     
     
         17 . The system of  claim 16 , wherein the diffusion barrier layer has a thickness of approximately 5 microns. 
     
     
         18 . The system of  claim 16 , further comprising a memory coupled to the circuit board. 
     
     
         19 . The system of  claim 16 , further comprising a central processing unit coupled to the circuit board. 
     
     
         20 . The system of  claim 16 , further comprising a logic unit coupled to the circuit board.