Determination of a match between data values stored by three or more arrays

Abstract

Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a plurality of arrays of memory cells formed on a single memory chip, each array of the plurality of arrays of memory cells configured to receive n portions of k data values that are deserialized from a data file comprising k data values via a respective bus of a plurality of kn-bit data buses such that the n portions of the deserialized data file each having k data values are redundantly stored over the plurality of arrays of memory cells; and   comparator circuitry configured to:
 compare the deserialized data files redundantly stored over the plurality of arrays to determine whether there is a match among the deserialized data files stored by more than a half of the plurality of arrays; and 
 output the matched data file stored in one array of the plurality of arrays. 
   
     
     
         2 . The apparatus of  claim 1 , wherein the comparator circuitry comprises a number of comparator components each coupled to a respective set of two arrays of the plurality and configured to determine a match between the data files redundantly stored over the two arrays of the respective set. 
     
     
         3 . The apparatus of  claim 2 , wherein the comparator circuitry further comprises a validation component that is coupled to at least a portion of the number of comparator components, and wherein the comparator circuitry is configured to determine the match among the deserialized data file stored by more than a half of the plurality of arrays using the validation component. 
     
     
         4 . The apparatus of  claim 1 , further comprising a serializer coupled to the comparator circuitry, and wherein:
 the comparator circuitry is configured to provide the matched data file stored in the one array to the serializer; and   the serializer is configured to reconstruct the received data file having the n portions into a single sequence of k data values.   
     
     
         5 . The apparatus of  claim 1 , wherein one array of the plurality of arrays is configured to receive the data file corresponding to the n portions of k data values via a kn-bit data bus. 
     
     
         6 . The apparatus of  claim 1 , wherein each array of the plurality of arrays is configured to receive the data file corresponding to the n portions of k data values via a separate and respective kn-bit data bus and wherein a copy function is subsequently performed to copy the data file stored in the one array to the other arrays of the plurality of arrays. 
     
     
         7 . A system, comprising:
 a plurality of arrays of memory cells formed on a single memory chip, wherein a data file is redundantly stored over the plurality of arrays in a deserialized from and as n portions each having k data values;   comparator circuitry coupled to the plurality of arrays; and   a serializer coupled to the comparator;   wherein the comparator circuitry is configured to:
 compare the data files redundantly stored over the plurality of arrays; and 
 access, in response to a determination of a match among the data files redundantly stored over at least a half of the plurality of arrays, one array of the plurality of arrays storing the matched data file to output the matched data file having the n portions to the serializer; and 
   wherein the serializer is configured to reconstruct the data file into a single sequence of k data values.   
     
     
         8 . The system of  claim 7 , wherein the comparator circuitry is coupled directly to a functionality or indirectly to the functionality through the serializer. 
     
     
         9 . The system of  claim 8 , wherein the comparator circuitry is configured provide, in response to a determination of no match among the data files redundantly stored over the plurality of arrays, a notification directly to the functionality. 
     
     
         10 . The system of  claim 9 , wherein the serializer is configured to provide, in response to the determination of a match among the data files redundantly stored over at least the half of the plurality of arrays, the serialized data file having k data values to the functionality without providing the notification. 
     
     
         11 . The system of  claim 8 , wherein the functionality is formed on a different memory chip than the single memory chip. 
     
     
         12 . The system of  claim 7 , wherein the serializer is formed on the single memory chip. 
     
     
         13 . A system, comprising:
 a plurality of arrays of memory cells;   a deserializer coupled to the plurality of arrays of memory cells and configured to:
 receive a data file having k data values; 
 deserialize the data file into a number of n portions each having k data values; and 
 provide the deserialized data file to the plurality of array of memory cells such that the deserialized data file is redundantly stored over the plurality of arrays; and 
   comparator circuitry coupled to the plurality of arrays of memory cells and configured to:
 compare the deserialized data files redundantly stored over the plurality of arrays to determine whether there is a match among the deserialized data files stored by more than a half of the plurality of arrays; and 
 output the matched data file stored in one array of the plurality of arrays. 
   
     
     
         14 . The system of  claim 13 , wherein:
 the plurality of arrays of memory cells is formed on an autonomous vehicle; and   the system further comprises a memory, the memory storing instructions executable for a failover functionality for execution responsive to determination of no match or a mismatch among the deserialized data file stored by more than the half of the plurality of arrays.   
     
     
         15 . The system of  claim 13 , wherein the deserializer is configured to receive the data file via a k-bit data bus. 
     
     
         16 . The system of  claim 13 , wherein the deserializer is configured to provide the deserialized data file to the plurality of arrays via one or more kn-bit data buses. 
     
     
         17 . The system of  claim 13 , wherein the deserialized data file is redundantly stored over a portion of the plurality of arrays and a size of the portion of the plurality of arrays is determined based on a size of the data file. 
     
     
         18 . The system of  claim 13 , wherein each array of the plurality of arrays corresponds to a different bank group, each different bank group having a plurality of memory banks formed on a single memory chip. 
     
     
         19 . The system of  claim 13 , wherein each array of the plurality of arrays corresponds to a different memory bank formed on a single memory chip. 
     
     
         20 . The system of  claim 13 , wherein each array of the plurality of arrays corresponds to a different section of a single memory bank formed on a single memory chip.