Architecture for monolithic 3d integration of semiconductor devices

Abstract

A three-dimensional (3D) integrated circuit (IC) includes a substrate having a substrate surface, a power rail provided in the substrate, and a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate. A wiring tier is provided in the substrate, and a second tier of semiconductor devices is provided in the substrate and positioned over the wiring tier along the thickness direction. The second tier of semiconductor devices is stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices. A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices. A second vertical interconnect structure extends upward from the wiring tier to the second tier of semiconductor devices to electrically connect the wiring tier to a device within the second tier of semiconductor devices.

What is claimed is: 
     
         1 . A three-dimensional (3D) integrated circuit (IC) comprising:
 a substrate having a substrate surface;   a power rail provided in the substrate;   a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate which is substantially perpendicular to said substrate surface;   a wiring tier provided in the substrate and positioned over the first tier of semiconductor devices along the thickness direction;   a second tier of semiconductor devices provided in the substrate and positioned over the wiring tier along the thickness direction, the second tier of semiconductor devices being stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices;   a first vertical interconnect structure extending downward from the wiring tier to the first tier of semiconductor devices along the thickness direction to electrically connect the wiring tier to a device within the first tier of semiconductor devices; and   a second vertical interconnect structure extending upward from the wiring tier to the second tier of semiconductor devices along the thickness direction to electrically connect the wiring tier to a device within the second tier of semiconductor devices.   
     
     
         2 . The 3D IC of  claim 1 , further comprising a third tier of semiconductor devices provided in the substrate and stacked on the second tier of semiconductor devices in the thickness direction. 
     
     
         3 . The 3D IC of  claim 2 , further comprising an intermediate power rail provided in the substrate and positioned over the second tier of semiconductor devices such that the intermediate power rail is positioned between the second and third tiers of semiconductor devices along the thickness direction. 
     
     
         4 . The 3D IC of  claim 3 , further comprising:
 a first power connection structure extending upward from the power rail to the first tier of semiconductor devices along the thickness direction to electrically connect the power rail to the device within the first tier of semiconductor devices,   a second power connection structure extending downward from the intermediate power rail to the second tier of semiconductor devices along the thickness direction to electrically connect the intermediate power rail to the device within the second tier of semiconductor devices, and   a third power connection structure extending upward from the intermediate power rail to the third tier of semiconductor devices along the thickness direction to electrically connect the intermediate power rail to a device within the third tier of semiconductor devices.   
     
     
         5 . The 3D IC of  claim 2 , wherein:
 the first tier of semiconductor devices comprises a first stacked pair of complementary field effect transistors sharing a common gate structure,   the second tier of semiconductor devices comprises a second stacked pair of complementary field effect transistors sharing a common gate structure,   the third tier of semiconductor devices comprises:
 a third stacked pair of complementary field effect transistors sharing a common gate structure, and 
 an additional transistor stacked over the third stacked pair of complementary field effect transistors; and 
   the first second and third stacked pairs of complementary field effect transistors are stacked in relation to one another.   
     
     
         6 . The 3D IC of  claim 5 , wherein:
 the first stacked pair of complementary field effect transistors has an n-over-p orientation,   the second stacked pair of complementary field effect transistors has a p-over-n orientation, and   the third stacked pair of complementary field effect transistors has an n-over-p orientation.   
     
     
         7 . The 3D IC of  claim 6 , wherein the third tier of semiconductor devices further comprises an n-type field effect transistor stacked on the third stacked pair of complementary field effect transistors. 
     
     
         8 . The 3D IC of  claim 7 , wherein:
 the first tier of semiconductor devices comprises a first logic circuit,   the second tier of semiconductor devices comprises a second logic circuit, and   the third tier of semiconductor devices comprises a memory circuit.   
     
     
         9 . The 3D IC of  claim 8 , wherein:
 the first logic circuit is an And-Or-Inverter (AOI) circuit,   the second logic circuit is an Exclusive-Or (XOR) circuit, and   the memory circuit is an SRAM circuit.   
     
     
         10 . The 3D IC of  claim 1 , further comprising an intermediate power rail provided in the substrate and positioned over the power rail along the thickness direction of the substrate.