Patterning oxidation resistant electrode in crossbar array circuits

Abstract

An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer.

What is claimed is: 
     
         1 . A method of manufacturing an RRAM-based crossbar array circuit comprising:
 providing a substrate;   forming a bottom electrode on the substrate;   forming a patterned mask layer on the bottom electrode;   thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma;   removing a gaseous status of the bottom electrode oxide by a first vacuum purge;   removing a solid status of the bottom electrode oxide by applying a second plasma;   removing the gaseous status of the bottom electrode oxide and the solid status of the bottom electrode oxide by a second vacuum purge to form a patterned bottom electrode;   removing the patterned mask layer;   forming a filament forming layer on the patterned bottom electrode; and   forming a top electrode on the filament forming layer, wherein the filament forming layer is configured to form a filament within the filament forming layer when applying a switching voltage upon the filament forming layer.   
     
     
         2 . The method as claimed in  claim 1 , wherein the first plasma comprises an oxygen plasma. 
     
     
         3 . The method as claimed in  claim 1 , wherein the second plasma comprises an argon plasma. 
     
     
         4 . The method as claimed in  claim 1 , wherein the thermal process comprises heating under a temperature between 350° C. and 450° C. 
     
     
         5 . The method as claimed in  claim 1 , wherein the substrate is made of a material selected from Si, SiO 2 , Si 3 N 4 , Al 2 O 3 , AN, or glass. 
     
     
         6 . The method as claimed in  claim 1 , wherein the bottom electrode layer is made of an oxidation resistance conductive material comprising Pt, Pd, Ir, a combinations thereof, or an alloy or other conductive materials thereof. 
     
     
         7 . The method as claimed in  claim 1 , wherein the bottom electrode layer is made of a material selected from a Ti/Pt layer, a Ti/Pd layer, or a Ti/(Pt, Pd) layer. 
     
     
         8 . The method as  claim 1 , wherein a thickness of the bottom electrode layer is between 10 nanometers and 30 nanometers. 
     
     
         9 . The method as claimed in  claim 1 , wherein a material of the top electrode comprises Pd, Pt, Ir, W, Ta, Hf, Nb, V, Ti, TiN, TaN, NbN, a combination thereof, or an alloy with any other conductive materials thereof. 
     
     
         10 . The method as claimed in  claim 1 , wherein a material of the filament forming layer comprises TaO x  (where x≤2.5), HfO x  (where x≤2), TiO x (where x≤2), ZrO x  (where x≤2), or a combination thereof. 
     
     
         11 . The method as claimed in  claim 1 , further comprises:
 forming an inter-layer dielectric layer or a thermal oxide layer on the substrate before forming the bottom electrode on the substrate, wherein a material of the thermal oxide layer comprises SiO 2 .   
     
     
         12 . The method as claimed in  claim 1 , wherein forming a patterned mask layer on the bottom electrode layer comprises:
 forming a mask layer on the bottom electrode layer;   forming a photo resist layer on the mask layer;   patterning the photo resist layer to be a patterned photo resist layer;   etching the mask layer by reactive-ion etching or ion-etch via the patterned photo resist layer to form the patterned mask layer; and   removing the patterned photo resist layer.   
     
     
         13 . The method as claimed in  claim 12 , wherein a material of the mask layer comprises SiO 2 . 
     
     
         14 . The method as claimed in  claim 13 , wherein a density of the mask layer is lower than that of the thermal oxide layer. 
     
     
         15 . The method as claimed in  claim 1 , further comprises:
 connecting the patterned bottom electrode to a first row wire; and   connecting the top electrode to a first column wire.