Method for preparing semiconductor package structure

Abstract

The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL.

What is claimed is: 
     
         1 . A method for preparing a semiconductor package structure, comprising:
 providing a first die;   bonding a second die to the first die, wherein the second die comprises a plurality of first conductors;   disposing a plurality of second conductors on the first die;   disposing a molding to encapsulate the first die, the second die and the plurality of second conductors;   disposing a redistribution layer (RDL) on the second die and the molding; and   disposing a plurality of connecting structures on the RDL.   
     
     
         2 . The method of  claim 1 , further comprising attaching the first die on a carrier substrate prior to the bonding of the second die to the first die. 
     
     
         3 . The method of  claim 2 , further comprising:
 singulating the RDL, the molding, the first die and the second die after the forming of the connecting structures to form a semiconductor package structure; and   detaching the semiconductor package structure from the carrier substrate.   
     
     
         4 . The method of  claim 1 , wherein the first die further comprises a plurality of conductive members. 
     
     
         5 . The method of  claim 4 , wherein the second die is bonded and electrically connected to the first die by the plurality of conductive members. 
     
     
         6 . The method of  claim 1 , further comprising removing a portion of the molding to expose a surface of the second die and surfaces of the plurality of second conductors prior to the forming of the RDL. 
     
     
         7 . The method of  claim 1 , wherein a die size of the first die is greater than a die size of the second die. 
     
     
         8 . The method of  claim 1 , wherein the first die is a logic die and the second die is a memory die. 
     
     
         9 . The method of  claim 1 , wherein the plurality of first conductors comprise a plurality of through silicon vias (TSVs). 
     
     
         10 . The method of  claim 1 , wherein the plurality of second conductors comprise a plurality of through molding vias (TMVs).