Hacking-Resistant Computer Design

Abstract

A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a network such as the Internet. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and hardware-protects it from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition.

What is claimed: 
     
         1 . An apparatus, designed to connect computers, comprising:
 a bus controller configured to be coupled to a first computer and at least one second computer;   wherein the bus controller is configured to receive a pull command from the first computer and to execute the pull command to read data from the at least one second computer through a bus and write the data read from the at least one second computer to at least one memory module of the first computer in a memory address range configured for data read from the at least one second computer;   wherein the bus controller is configured to receive a push command from the first computer and to execute the push command to send data to the at least one second computer through the bus;   wherein the bus controller will not permit a push command from the at least one second computer to the first computer;   wherein the bus controller will not permit a pull command from the at least one second computer to the first computer; and   wherein the hardware circuitry of the bus controller does not permit the at least one second computer to access the at least one memory module of the first computer.