US2022037532A1PendingUtilityA1
Semiconductor device and manufacturing method of the same
Est. expiryApr 13, 2035(~8.7 yrs left)· nominal 20-yr term from priority
Inventors:Satoshi ToriumiTakashi HamadaTetsunori MaruyamaYuki ImotoYuji AsanoRyunosuke HondaShunpei Yamazaki
H10B 41/70H10D 64/691H10D 87/00H10D 86/481H10D 30/6755H10D 86/60H10D 88/01H10D 88/00H10D 86/423H10D 84/038H10D 62/80H10D 30/6757H10D 30/6739H10D 30/6734H10D 30/6729H10D 30/673H10F 39/184H10F 39/182H01L 27/0688H01L 29/24H01L 29/78696H01L 27/14645H01L 29/78648H01L 27/14649H01L 21/8221H01L 29/7869H01L 29/4908H01L 27/1225H01L 27/1156H01L 29/42384H01L 29/41733H01L 29/517H01L 27/1207
75
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Claims
Abstract
A minute transistor is provided that includes a first insulator, a second insulator, a first, conductor, a second conductor, and third conductor, in which an angle is formed between a side surface of the first insulator and a top surface of the first conductor, and a length between the first conductor and a surface of the second conductor closest to the first conductor is at least greater than a length between the first conductor and the third conductor.
Claims
exact text as granted — not AI-modified1 . A semiconductor device, comprising:
a semiconductor over a substrate; a first conductor and a second conductor over the semiconductor; a first insulator over the first conductor and the second conductor; a second insulator over the semiconductor; a third insulator over the second insulating; a third conductor over the third insulating; and a fourth conductor over the third conductor, wherein the third insulator has a region in contact with a side surface of the first insulator, wherein the third conductor and the fourth conductor have a function as a gate electrode, wherein the semiconductor has a first region overlapping a bottom surface of the first conductor, a second region overlapping a bottom surface of the second conductor, and a third region overlapping a bottom surface of the third conductor, and wherein a length between a top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region.
2 . A semiconductor device, comprising:
a semiconductor over a substrate; a first conductor and a second conductor over the semiconductor; a first insulator over the first conductor and the second conductor; a second insulator over the semiconductor; a third insulator over the second insulating; a third conductor over the third insulating; a fourth conductor over the third conductor; and a fifth conductor between the substrate and the semiconductor, wherein the third insulator has a region in contact with a side surface of the first insulator, wherein the third conductor and the fourth conductor have a function as a gate electrode, wherein the fifth conductor has a region overlapping with the third conductor and the fourth conductor, wherein the semiconductor has a first region overlapping a bottom surface of the first conductor, a second region overlapping a bottom surface of the second conductor, and a third region overlapping a bottom surface of the third conductor, and wherein a length between a top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region.
3 . A semiconductor device, comprising:
a semiconductor over a substrate; a first conductor and a second conductor over the semiconductor; a first insulator over the first conductor and the second conductor; a second insulator over the semiconductor; a third insulator over the second insulating; a third conductor over the third insulating; and a fourth conductor over the third conductor, wherein the third insulator has a region in contact with a side surface of the first insulator, wherein the semiconductor has a first region overlapping a bottom surface of the first conductor, a second region overlapping a bottom surface of the second conductor, and a third region overlapping a bottom surface of the third conductor, and wherein a length between a top surface of the semiconductor and the bottom surface of the third conductor is greater than the length between the first region and the third region.
4 . The semiconductor device according to claim 1 , wherein the semiconductor is an oxide semiconductor.
5 . The semiconductor device according to claim 2 , wherein the semiconductor is an oxide semiconductor.
6 . The semiconductor device according to claim 3 , wherein the semiconductor is an oxide semiconductor.
7 . The semiconductor device according to claim 4 , wherein the oxide semiconductor comprises indium, gallium, and zinc.
8 . The semiconductor device according to claim 5 , wherein the oxide semiconductor comprises indium, gallium, and zinc.
9 . The semiconductor device according to claim 6 , wherein the oxide semiconductor comprises indium, gallium, and zinc.
10 . The semiconductor device according to claim 7 , wherein the oxide semiconductor is polycrystalline, a CAAC-OS, a nc-OS, or an a-like OS.
11 . The semiconductor device according to claim 8 , wherein the oxide semiconductor is polycrystalline, a CAAC-OS, a nc-OS, or an a-like OS.
12 . The semiconductor device according to claim 9 , wherein the oxide semiconductor is polycrystalline, a CAAC-OS, a nc-OS, or an a-like OS.Join the waitlist — get patent alerts
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