Interlayer connection of stacked microelectronic components

Abstract

Representative techniques and devices including process steps may be employed to form a common interconnection of a multi-die or multi-wafer stack. Each device of the stack includes a conductive pad disposed at a predetermined relative position on a surface of the device. The devices are stacked to vertically align the conductive pads. A through-silicon via is formed that electrically couples the conductive pads of each device of the stack.

What is claimed is: 
     
         1 . A microelectronic assembly, comprising:
 a plurality of microelectronic substrates, comprising at least three microelectronic substrates, direct bonded to form a vertical stack of microelectronic substrates;   a conductive pad disposed at a first relative position on a surface of each of the plurality of microelectronic substrates, the conductive pad of each subsequent microelectronic substrate of the vertical stack of microelectronic substrates is intentionally offset a predetermined distance relative to the conductive pad on the surface of a previously placed microelectronic substrate of the vertical stack of microelectronic substrates; and   a cavity extending through an interior area of the conductive pad of at least all but one of the plurality of microelectronic substrates.   
     
     
         2 . The microelectronic assembly of  claim 1 , wherein at least a portion of the conductive pad on the surface of each of the plurality of microelectronic substrates is vertically aligned. 
     
     
         3 . The microelectronic assembly of  claim 1 , wherein the cavity is filled with a conductive material to form a through silicon via (TSV) common to each of the plurality of microelectronic substrates of the vertical stack of microelectronic substrates, the TSV comprising an interlayer connection electrically coupling the conductive pad on the surface of each of the plurality of microelectronic substrates. 
     
     
         4 . The microelectronic assembly of  claim 1 , wherein an exterior perimeter of the conductive pad on the surface of each of the plurality of microelectronic substrates has a first predetermined size and shape and wherein the interior area of the conductive pad on the surface of the at least all but one of the microelectronic substrates has a second predetermined size and shape. 
     
     
         5 . The microelectronic assembly of  claim 4 , wherein the conductive pad on the surface of the at least all but one of the microelectronic substrates has an “O,” a “C,” a “D,” a “G,” or a “U” shape. 
     
     
         6 . The microelectronic assembly of  claim 4 , wherein the second predetermined size and shape comprises a polygon, a geometric shape, an eccentric shape, an irregular shape, or a multi-faceted shape. 
     
     
         7 . The microelectronic assembly of  claim 1 , wherein a size of the interior area of the conductive pad on the surface of the at least all but one of the microelectronic substrates is not uniform throughout the vertical stack of microelectronic substrates. 
     
     
         8 . The microelectronic assembly of  claim 7 , wherein a size of the interior area of the conductive pad on the surface of the at least all but one of the microelectronic substrates progressively increases with each of the microelectronic substrates of the vertical stack, from a microelectronic substrate at a bottom of the vertical stack to a microelectronic substrate at a top of the vertical stack. 
     
     
         9 . The microelectronic assembly of  claim 1 , wherein the intentional offset of each subsequent microelectronic substrate is in a first offset direction relative to the previously placed microelectronic substrate. 
     
     
         10 . The microelectronic assembly of  claim 1 , wherein the predetermined distance is larger than an average die placement error of die placement tools used to stack the plurality of microelectronic substrates to form the vertical stack. 
     
     
         11 . The microelectronic assembly of  claim 1 , wherein the at least three microelectronic substrates are direct bonded using an ambient temperature direct bonding technique without adhesives. 
     
     
         12 . A microelectronic assembly, comprising:
 a plurality of microelectronic substrates, comprising at least three microelectronic substrates, stacked to form a vertical stack of microelectronic substrates;   a conductive pad disposed on a surface of each of the plurality of microelectronic substrates, the conductive pad on the surface of each subsequent microelectronic substrate of the plurality of microelectronic substrates intentionally offset a predetermined distance relative to the conductive pad on the surface of a previously placed microelectronic substrate of the plurality of microelectronic substrates; and   a cavity extending through an interior area of the conductive pad of at least all but one of the microelectronic substrates of the plurality of microelectronic substrates.   
     
     
         13 . The microelectronic assembly of  claim 12 , wherein at least a portion of the conductive pad on the surface of each of the plurality of microelectronic substrates is vertically aligned. 
     
     
         14 . The microelectronic assembly of  claim 12 , wherein the cavity is filled with a conductive material to form a through silicon via (TSV) common to each of the plurality of microelectronic substrates of the vertical stack of microelectronic substrates, the TSV comprising an interlayer connection electrically coupling the conductive pad on the surface of each of the plurality of microelectronic substrates. 
     
     
         15 . The microelectronic assembly of  claim 12 , wherein the cavity is adjacent to a portion of the conductive pad on the surface of the at least all but one of the plurality of microelectronic substrates. 
     
     
         16 . The microelectronic assembly of  claim 12 , wherein the interior area of the conductive pad of each microelectronic substrate of the stack has a different maximum dimension. 
     
     
         17 . The microelectronic assembly of  claim 12 , wherein the interior area of the conductive pad of each subsequent microelectronic substrate of the plurality of microelectronic substrates of the vertical stack has a larger maximum dimension than a maximum dimension of the interior area of the conductive pad of a previously placed microelectronic substrate of the plurality of microelectronic substrates. 
     
     
         18 . The microelectronic assembly of  claim 12 , wherein the interior area of the conductive pad of each of the plurality of microelectronic substrates of the stack has a predetermined size and shape comprising a polygon, a geometric shape, an eccentric shape, an irregular shape, or a multi-faceted shape. 
     
     
         19 . A microelectronic assembly, comprising:
 a plurality of microelectronic substrates, comprising at least three microelectronic substrates, stacked to form a vertical stack of microelectronic substrates, each of the microelectronic substrates of the vertical stack of microelectronic substrates being misaligned with respect to at least one other microelectronic substrate of the vertical stack of microelectronic substrates;   a conductive pad disposed at a first relative position on a surface of each of the plurality of microelectronic substrates;   a cavity extending through an interior area of the conductive pad of at least all but one of the plurality of microelectronic substrates; and   a conductive material filled within the cavity to form a through silicon via (TSV) common to each of the microelectronic substrates of the vertical stack of microelectronic substrates, the TSV comprising an interlayer connection electrically coupling the conductive pad on the surface of each of the plurality of microelectronic substrates.   
     
     
         20 . The microelectronic assembly of  claim 19 , wherein the conductive pad on the surface of each of the plurality of microelectronic substrates is misaligned with respect to at least one other conductive pad on the surface of another microelectronic substrate of the vertical stack of microelectronic substrates. 
     
     
         21 . The microelectronic assembly of  claim 19 , wherein at least a portion of the conductive pad on the surface of each of the plurality of microelectronic substrates is vertically aligned. 
     
     
         22 . The microelectronic assembly of  claim 19 , wherein a size of the interior area of the conductive pad on the surface of the at least all but one of the plurality of microelectronic substrates is not uniform. 
     
     
         23 . The microelectronic assembly of  claim 21 , wherein the size of the interior area gets progressively larger from a microelectronic substrate at a bottom of the vertical stack to a microelectronic substrate at a top of the vertical stack.