Digital circuit having correcting circuit and electronic apparatus thereof

Abstract

Provided is a digital circuit ( 30 ) that comprises: a switching circuit ( 31 ) having first transistors ( 32, 33 ) supplied with power supply potentials (VDD, VSS); correcting circuits ( 34, 36 ) connected between an input terminal (IN) inputted with an input signal and control terminals (gates) of the first transistors; capacitors (C 2, C 3 ) connected between the control terminals and the input terminal; diode-connected second transistors ( 35, 37 ) that are provided between nodes (N 5, N 6 ) between the capacitors and the control terminals and the power supply potentials and have the substantially sanle threshold voltage as the first transistors; and switches (SW 2, SW 3 ) connected in series with the second transistors.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor;   a first switch; and   a capacitor,   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein the one of the source and the drain of the first transistor is electrically connected to an output terminal,   wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,   wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor without through any transistor,   wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the first switch without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the first switch without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the capacitor without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the capacitor without through any switch,   wherein a second terminal of the first switch is electrically connected to the second wiring,   wherein a second terminal of the capacitor is electrically connected to an input terminal,   wherein the third transistor is configured to charge the capacitor,   wherein a threshold voltage of the first transistor and a threshold voltage of the third transistor are substantially the same, and   wherein a size of the first transistor is different from a size of the third transistor.   
     
     
         3 . The semiconductor device according to  claim 2 ,
 wherein a first power supply potential is supplied to the first wiring, and   wherein a second power supply potential is supplied to the second wiring.   
     
     
         4 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor;   a first switch; and   a capacitor,   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein the one of the source and the drain of the first transistor is electrically connected to an output terminal,   wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,   wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,   wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor without through any transistor,   wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the first switch without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the first switch without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the capacitor without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the capacitor without through any switch,   wherein a second terminal of the first switch is electrically connected to the second wiring,   wherein a second terminal of the capacitor is electrically connected to an input terminal,   wherein the third transistor is configured to charge the capacitor in a first period,   wherein when the third transistor is off, a potential of the input terminal is changed in a second period after the first period,   wherein a threshold voltage of the first transistor and a threshold voltage of the third transistor are substantially the same, and   wherein a size of the first transistor is different from a size of the third transistor.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein a first power supply potential is supplied to the first wiring, and   wherein a second power supply potential is supplied to the second wiring.   
     
     
         6 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor;   a first switch; and   a capacitor,   wherein the first transistor is configured to control conduction and non-conduction between a first wiring and an output terminal,   wherein the second transistor is configured to control conduction and non-conduction between a second wiring and the output terminal,   wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor without through any transistor,   wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the first switch without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the first switch without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the capacitor without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the capacitor without through any switch,   wherein a second terminal of the first switch is electrically connected to the second wiring,   wherein a second terminal of the capacitor is electrically connected to a third wiring,   wherein a clock signal is supplied to the third wiring,   wherein the third transistor is configured to charge the capacitor,   wherein a threshold voltage of the first transistor and a threshold voltage of the third transistor are substantially the same, and   wherein a size of the first transistor is different from a size of the third transistor.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein a first power supply potential is supplied to the first wiring, and   wherein a second power supply potential is supplied to the second wiring.   
     
     
         8 . A semiconductor device comprising:
 a first transistor;   a second transistor;   a third transistor;   a first switch; and   a capacitor,   wherein the first transistor is configured to control conduction and non-conduction between a first wiring and an output terminal,   wherein the second transistor is configured to control conduction and non-conduction between a second wiring and the output terminal,   wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor without through any transistor,   wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the first switch without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the first switch without through any switch,   wherein the gate of the first transistor is electrically connected to a first terminal of the capacitor without through any transistor,   wherein the gate of the first transistor is electrically connected to the first terminal of the capacitor without through any switch,   wherein a second terminal of the first switch is electrically connected to the second wiring,   wherein a second terminal of the capacitor is electrically connected to a third wiring,   wherein a clock signal is supplied to the third wiring,   wherein the third transistor is configured to charge the capacitor in a first period,   wherein when the third transistor is off, the clock signal is changed in a second period after the first period,   wherein a threshold voltage of the first transistor and a threshold voltage of the third transistor are substantially the same, and   wherein a size of the first transistor is different from a size of the third transistor.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein a first power supply potential is supplied to the first wiring, and   wherein a second power supply potential is supplied to the second wiring.