Packaged semiconductor assemblies and methods for manufacturing such assemblies

Abstract

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

We claim: 
     
         1 . A stacked semiconductor assembly, comprising:
 a first semiconductor package having a first die and a first redistribution structure attached to the first die, wherein the first semiconductor package has a first footprint, and wherein the first redistribution structure includes a first bond site at a periphery of the first semiconductor package having a first inner edge;   a second semiconductor package carried by the first semiconductor package, the second semiconductor package having a second die generally identical to the first die and a second redistribution structure attached to the second die, wherein the second package has a second footprint smaller than the first footprint, and wherein the second redistribution structure includes a second bond site at a periphery of the second semiconductor package having a second inner edge aligned with the first inner edge along an axis normal to a surface of the first bond site;   an interconnect structure electrically connecting the first and second redistribution structures; and   an encapsulant disposed at least partially around the interconnect structure and the first and second bond sites.   
     
     
         2 . The stacked semiconductor assembly of  claim 1  wherein a portion of the second redistribution structure of the second die is exposed through an opening in the encapsulant. 
     
     
         3 . The stacked semiconductor assembly of  claim 2 , further comprising a conductive member electrically coupled to the portion of the second redistribution structure exposed through the opening in the encapsulant. 
     
     
         4 . The stacked semiconductor assembly of  claim 1  wherein the interconnect structure includes a wire bond attached directly to the first and second bond sites. 
     
     
         5 . The stacked semiconductor assembly of  claim 1  wherein the interconnect structure includes a conductive link disposed between the first and second bond sites. 
     
     
         6 . The stacked semiconductor assembly of  claim 1 , further comprising an adhesive material attaching the first semiconductor package to the second semiconductor package. 
     
     
         7 . The stacked semiconductor assembly of  claim 1  wherein the second package is positioned on the first semiconductor package with the second bond site at least partially overlapping the first bond site. 
     
     
         8 . A stacked semiconductor assembly, comprising:
 a first package including a first die having a first peripheral edge and a first bond site at a periphery of the first package, wherein the first package has a first footprint;   a second package carried by the first package, the second package including a second die generally identical in size to the first die and a second bond site at a periphery of the second package, wherein the second package has a second footprint smaller than the first footprint, and wherein the second die has a second peripheral edge aligned with the first peripheral edge along an axis generally transverse to the first and second dies;   an interconnect structure electrically connecting the first and second bond sites; and   an encapsulant disposed at least partially around the interconnect structure and the first and second bond sites.   
     
     
         9 . The stacked semiconductor assembly of  claim 8  wherein the first package further includes a first redistribution structure electrically connected to the first die and the first bond site, and wherein the second package further includes a second redistribution structure electrically connected to the second die and the second bond site. 
     
     
         10 . The stacked semiconductor assembly of  claim 9  wherein a portion of the second die redistribution structure is accessible through an opening in the encapsulant. 
     
     
         11 . The stacked semiconductor assembly of  claim 9  wherein the first die includes a first die bond site electrically coupled to the first redistribution structure, and wherein the second die includes a second die bond site electrically coupled to the first redistribution structure and aligned with the first die bond site. 
     
     
         12 . The stacked semiconductor assembly of  claim 8  wherein the first bond site is covered by the encapsulant. 
     
     
         13 . The stacked semiconductor assembly of  claim 8  wherein the second package further includes a third bond site coupled to the second bond site, and wherein the third bond site is accessible through an opening in the encapsulant. 
     
     
         14 . The stacked semiconductor assembly of  claim 8  wherein the interconnect structure includes a wire bond attached directly to the first and second bond sites. 
     
     
         15 . The stacked semiconductor assembly of  claim 8  wherein the interconnect structure includes a conductive link disposed between the first and second bond sites. 
     
     
         16 . A stacked semiconductor assembly, comprising:
 a first package, the first package including a first die and a first bond site adjacent a peripheral edge of the first package;   a second package carried by the first package, the second package including a second die generally identical the first die and a second bond site adjacent a peripheral edge of the second package, and wherein the second bond site at least partially overlaps with the first bond site; and   an interconnect structure electrically coupling the first bond site and the second bond site.   
     
     
         17 . The stacked semiconductor assembly of  claim 16  wherein the first package has a first footprint, and wherein the second package has a second footprint smaller than the first footprint. 
     
     
         18 . The stacked semiconductor assembly of  claim 16 , further comprising an encapsulant disposed at least partially around the interconnect structure, the first bond site, and the second bond site. 
     
     
         19 . The stacked semiconductor assembly of  claim 16  wherein the second package further includes a redistribution layer electrically coupling the second die to the second bond site, and wherein the stacked semiconductor assembly further comprises an external conductive member electrically coupled to the redistribution layer. 
     
     
         20 . The stacked semiconductor assembly of  claim 16  wherein the first package further includes a first insulating material at least partially surrounding the first die, and wherein the second die further includes a second insulating material at least partially surrounding the second die.