Asynchronous Non-Linear Control of Digital Linear Voltage Regulator

Abstract

A digital low dropout (LDO) voltage regulator enabling on-chip fine-grain power management in multi-core microprocessor and system-on-a-chip platforms to increase system level energy efficiency. Its design synthesizability with automatic placement and routing enables per-core dynamic voltage and frequency scaling with quick design turnaround. To enable per-core voltage regulation, the digital LDO is designed in a 65 nm complementary metal-oxide-semiconductor process. It exhibits core-level high load current driving capability of up to 125 mA and a large voltage regulation range of 0.15 V to 1.15 V.

What is claimed is: 
     
         1 . A voltage regulator comprising:
 an output configured to provide an output voltage;   power transistors configured to switch between an on state and an off state;   power regulation circuitry configured switch, synchronously with the clock, the power transistors;   load sensing circuitry configured to sense, asynchronously with the clock, a decrease in the output voltage; and   control circuitry configured to transition, asynchronously with the clock, power transistors in the off state to the on state.   
     
     
         2 . The voltage regulator of  claim 1 , wherein the control circuitry is configured to transition, asynchronously with the clock, every power transistor in the voltage regulator in the off state to the on state. 
     
     
         3 . The voltage regulator of  claim 1 , wherein the load sensing circuitry comprises a clockless comparator. 
     
     
         4 . The voltage regulator of  claim 1 , wherein the load sensing circuitry comprises:
 an active load differential amplifier;   a common source amplifier; and   fast slew rate registers.   
     
     
         5 . The voltage regulator of  claim 1 , wherein the control circuitry comprises shift registers;
 wherein an output of the shift registers is in communication with the power transistors; and   wherein the shift registers each comprise a reset input.   
     
     
         6 . The voltage regulator of  claim 1 , wherein the voltage regulator is configured to exhibit core-level load current driving capability of up to approximately 125 mA, and a voltage regulation range of approximately 0.15 V to approximately 1.15 V. 
     
     
         7 . The voltage regulator of  claim 1 , wherein the voltage regulator is configured to have a peak current efficiency of greater than approximately 99.5% at a load of approximately 4 mA and approximately 1 nF load decoupling capacitance. 
     
     
         8 . The voltage regulator of  claim 1 , wherein the voltage regulator is configured to have a nominal supply voltage of approximately 1.2 V. 
     
     
         9 . The voltage regulator of  claim 1 , wherein the voltage regulator is configured to deliver a maximum load current of approximately 125 mA at a dropout voltage of approximately 600 mV occupying a total area of approximately 0.061 mm 2  excluding decoupling capacitor area. 
     
     
         10 . The voltage regulator of  claim 1 , wherein the voltage regulator is configured to provide a regulated output voltage from approximately 0.15 V to approximately 1.15 V with a minimum operational dropout voltage of approximately 50 mV. 
     
     
         11 . A voltage regulator comprising:
 an output configured to provide an output voltage;   power transistors configured to switch between an on state and an off state;   shift registers configured to control the switching of the power transistors, wherein at least a portion of the shift registers each comprise a reset input;   a clockless comparator configured to compare the output voltage to a reference voltage, wherein the clockless comparator is in communication with at least a portion of the reset inputs.   
     
     
         12 . The voltage regulator of  claim 11 , wherein the voltage regulator is configured to exhibit core-level load current driving capability of up to approximately 125 mA, and a voltage regulation range of approximately 0.15 V to approximately 1.15 V. 
     
     
         13 . The voltage regulator of  claim 11 , wherein the voltage regulator is configured to have a peak current efficiency of greater than approximately 99.5% at a load of approximately 4 mA and approximately 1 nF load decoupling capacitance. 
     
     
         14 . The voltage regulator of  claim 11 , wherein the voltage regulator is configured to have a nominal supply voltage of approximately 1.2 V. 
     
     
         15 . The voltage regulator of  claim 11 , wherein the voltage regulator is configured to deliver a maximum load current of approximately 125 mA at a dropout voltage of approximately 600 mV occupying a total area of approximately 0.061 mm 2  excluding decoupling capacitor area. 
     
     
         16 . The voltage regulator of  claim 11 , wherein the voltage regulator is configured to provide a regulated output voltage from approximately 0.15 V to approximately 1.15 V with a minimum operational dropout voltage of approximately 50 mV. 
     
     
         17 . A method for asynchronous voltage recovery comprising:
 providing a voltage regulator comprising digital power transistors, resettable registers, and a voltage comparator;   comparing, with the voltage comparator, an output voltage of the voltage regulator to a reference voltage;   providing, by the comparator, a reset signal to the resettable registers;   providing, by the resettable registers, an asynchronous control signal; and   activating, in response to the asynchronous control signal, each of the digital power transistors to an on state.   
     
     
         18 . The method of  claim 17  further comprising exhibiting core-level load current driving capability of up to approximately 125 mA, and a voltage regulation range of approximately 0.15 V to approximately 1.15 V. 
     
     
         19 . The method of  claim 17 , wherein the voltage regulator is configured to have a peak current efficiency of greater than approximately 99.5% at a load of approximately 4 mA and approximately 1 nF load decoupling capacitance. 
     
     
         20 . The method of  claim 17 , wherein the voltage regulator is configured to have a nominal supply voltage of approximately 1.2 V. 
     
     
         21 . The method of  claim 17 , wherein the voltage regulator is configured to deliver a maximum load current of approximately 125 mA at a dropout voltage of approximately 600 mV occupying a total area of approximately 0.061 mm 2  excluding decoupling capacitor area. 
     
     
         22 . The method of  claim 17 , wherein the voltage regulator is configured to provide a regulated output voltage from approximately 0.15 V to approximately 1.15 V with a minimum operational dropout voltage of approximately 50 mV.