US2022005731A1PendingUtilityA1

Etch stop layer removal for capacitance reduction in damascene top via integration

Assignee: IBMPriority: Apr 17, 2020Filed: Sep 20, 2021Published: Jan 6, 2022
Est. expiryApr 17, 2040(~13.7 yrs left)· nominal 20-yr term from priority
H10W 20/4437H10W 20/438H10W 20/083H10W 20/056H10W 20/42H10W 20/074H10W 20/063H01L 23/5226H01L 21/76829H01L 21/76877H01L 21/76805
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Claims

Abstract

A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An interconnect structure comprising:
 at least one first-level interconnect in a dielectric layer; and   at least one second-level interconnect in a replacement dielectric layer stacked on the dielectric layer,   wherein the replacement dielectric layer directly contacts the dielectric layer.   
     
     
         2 . The interconnect structure of  claim 1 , wherein the replacement dielectric layer excludes etch-induced damages or defects adjacent to the conductive via. 
     
     
         3 . The interconnect structure of  claim 2 , wherein the at least one second-level interconnect directly contacts the at least one first-level interconnect. 
     
     
         4 . The interconnect structure of  claim 3 , wherein the interconnect structure completely excludes an etch stop layer between the dielectric layer and the replacement dielectric layer. 
     
     
         5 . The interconnect structure of  claim 2 , wherein the dielectric layer has a first dielectric constant value that is less than 3.9. 
     
     
         6 . The interconnect structure of  claim 5 , wherein the replacement dielectric layer has a second dielectric constant value that is less than the first dielectric constant. 
     
     
         7 . The interconnect structure of  claim 6 , wherein the at least one first-level interconnect and the at least one second-level interconnect each comprise a metal material. 
     
     
         8 . The interconnect structure of  claim 2 , wherein the at least one first-level interconnect is a conductive line comprising a metal material and the at least one second-level interconnect is a conductive via comprising a metal material.

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