Dynamically Reconfigurable Memory Subsystem For Graphics Processors

Abstract

By predicting future memory subsystem request behavior based on live memory subsystem usage history collection, a preferred setting for handling predicted upcoming request behavior may be generated and used to dynamically reconfigure the memory subsystem. This mechanism can be done continuously and in real time during to ensure active tracking of system behavior.

1 . (canceled) 
     
     
         2 . A graphics processing unit comprising:
 an interface to couple the graphics processing unit to a processor;   a plurality of texture units;   a plurality of register files;   a plurality of load/store units;   a plurality of graphics processing cores coupled to the plurality of register files; and   a shared cache memory coupled to the plurality of graphics processing cores, wherein the shared cache memory is to control replacement of data of an access request received from one of the plurality of graphics processing cores, based at least in part on a marker associated with the access request, the marker to indicate a replacement algorithm for the access request.   
     
     
         3 . The graphics processing unit of  claim 2 , wherein the shared cache memory is to provide differentiated cache service parameters to different access requests based at least in part on different markers associated with the different access requests. 
     
     
         4 . The graphics processing unit of  claim 2 , wherein the shared cache memory comprises a plurality of partitions. 
     
     
         5 . The graphics processing unit of  claim 2 , wherein the shared cache memory is to receive a plurality of access requests, each of the plurality of access requests having a marker to indicate a replacement algorithm for the corresponding access request. 
     
     
         6 . The graphics processing unit of  claim 2 , wherein the shared cache memory is to control replacement operations on a per access request basis. 
     
     
         7 . The graphics processing unit of  claim 2 , wherein the marker comprises a quality of service marker. 
     
     
         8 . The graphics processing unit of  claim 2 , further comprising scheduler logic to schedule groups of instructions. 
     
     
         9 . The graphics processing unit of  claim 2 , further comprising a plurality of arithmetic logic units to perform operations on integer data types. 
     
     
         10 . The graphics processing unit of  claim 2 , further comprising at least one memory unit. 
     
     
         11 . The graphics processing unit of  claim 5 , wherein the at least one memory unit comprises a load and store unit. 
     
     
         12 . The graphics processing unit of  claim 2 , further comprising at least one special function unit. 
     
     
         13 . The graphics processing unit of  claim 2 , wherein the graphics processing unit comprises a single instruction multiple thread processor. 
     
     
         14 . The graphics processing unit of  claim 2 , wherein the processor and the graphics processing unit are integrated in a single package. 
     
     
         15 . A non-transitory storage medium comprising instructions that when executed cause a shared cache memory of a graphics processing unit (GPU) to:
 receive, in the shared cache memory of the GPU, a first access request for first data from a first graphics processing core of a plurality of graphics processing cores coupled to the shared cache memory, the first access request having a first marker to indicate a first replacement algorithm for the first access request; and   perform, in the shared cache memory, the first access request for the first data, and replace the first data in the shared cache memory according to the first replacement algorithm;   receive, in the shared cache memory, a second access request for second data from the first graphics processing core, the second access request having a second marker to indicate a second replacement algorithm for the second access request, the second replacement algorithm different than the first replacement algorithm; and   perform, in the shared cache memory, the second access request for the second data, and replace the second data in the shared cache memory according to the second replacement algorithm.   
     
     
         16 . The non-transitory storage medium of  claim 15 , further comprising instructions that when executed cause the shared cache memory to replace the first data according to the first replacement algorithm comprising a least recently used algorithm. 
     
     
         17 . The non-transitory storage medium of  claim 16 , further comprising instructions that when executed cause the shared cache memory to replace the second data according to the second replacement algorithm comprising a least frequently used algorithm. 
     
     
         18 . A method comprising:
 receiving, in a shared cache memory of a graphics processing unit (GPU), a first access request for first data from a first graphics processing core of a plurality of graphics processing cores coupled to the shared cache memory, the first access request having a first marker to indicate a first replacement algorithm for the first access request; and   performing, in the shared cache memory, the first access request for the first data, and replacing the first data in the shared cache memory according to the first replacement algorithm;   receiving, in the shared cache memory, a second access request for second data from the first graphics processing core, the second access request having a second marker to indicate a second replacement algorithm for the second access request, the second replacement algorithm different than the first replacement algorithm; and   performing, in the shared cache memory, the second access request for the second data, and replacing the second data in the shared cache memory according to the second replacement algorithm.   
     
     
         19 . The method of  claim 18 , further comprising replacing the first data according to the first replacement algorithm comprising a least recently used algorithm. 
     
     
         20 . The method of  claim 19 , further comprising replacing the second data according to the second replacement algorithm comprising a least frequently used algorithm.