Weight storage using memory device

Abstract

Methods, systems, and devices for mimicking neuro-biological architectures that may be present in a nervous system are described herein. A memory device may include a memory unit configured to store a value. A memory unit may include a first memory cell (e.g., an aggressor memory cell) and a plurality of other memory cells (e.g., victim memory cells). The memory unit may use thermal disturbances of the victim memory cells that may be based on an access operation to store the analog value. Thermal energy output by the aggressor memory cell during an access operation (e.g., a write operation) may cause the state of the victim memory cells to alter based on thermal relationship between the aggressor memory cell and at least some of the victim memory cells. The memory unit may be read by detecting and combining the weights of the victim memory cells during a read operation.

1 . (canceled) 
     
     
         2 . A method, comprising:
 selecting at least one memory cell of a neural memory unit for a read operation, the neural memory unit comprising a primary memory cell and a plurality of secondary memory cells thermally coupled with the primary memory cell;   biasing one or more word lines coupled with the neural memory unit based at least in part on selecting the at least one memory cell;   detecting one or more signals generated on one or more digit lines coupled with the neural memory unit based at least in part on biasing the one or more word lines; and   determining an analog value stored by the neural memory unit based at least in part on detecting the one or more signals generated on the one or more digit lines.   
     
     
         3 . The method of  claim 2 , further comprising:
 detecting a leakage current associated with at least one digit line of the one or more digit lines, wherein detecting the one or more signals is based at least in part on detecting the leakage current.   
     
     
         4 . The method of  claim 3 , further comprising:
 biasing one or more unselected word lines with a voltage during the read operation, wherein detecting the leakage current associated with each digit line is based at least in part on biasing the one or more unselected word lines.   
     
     
         5 . The method of  claim 2 , further comprising:
 determining a weight value for each signal generated on each digit line of the one or more digit lines; and   combining the determined weight values for each signal generated on each digit line, wherein determining the analog value is based at least in part on combining the determined weight values.   
     
     
         6 . The method of  claim 2 , further comprising:
 precharging the one or more digit lines during the read operation, wherein detecting the one or more signals is based at least in part on precharging the one or more digit lines.   
     
     
         7 . The method of  claim 6 , wherein precharging the one or more digit lines further comprises:
 precharging a first digit line of the one or more digit lines during the read operation, wherein the first digit line is coupled with at least a first secondary memory cell;   precharging a second digit line of the one or more digit lines during the read operation, wherein the second digit line is coupled with the primary memory cell and more than one secondary memory cell; and   precharging a third digit line of the one or more digit lines during the read operation, wherein the third digit line is coupled with at least a second secondary memory cell, and wherein precharging the one or more digit lines is based at least in part on precharging the first digit line, the second digit line, and the third digit line.   
     
     
         8 . The method of  claim 2 , further comprising:
 biasing a first word line of the one or more word lines during the read operation, wherein the first word line is coupled with at least a first secondary memory cell;   biasing a second word line of the one or more word lines during the read operation, wherein the second word line is coupled with the primary memory cell and more than one secondary memory cell; and   biasing a third word line of the one or more word lines during the read operation, wherein the third word line is coupled with at least a second secondary memory cell, and wherein biasing the one or more word lines is based at least in part on biasing the first word line, the second word line, and the third word line.   
     
     
         9 . The method of  claim 2 , wherein:
 each secondary memory cell is thermally coupled with the primary memory cell according to a thermal relationship; and   the thermal relationship between the primary memory cell and a first secondary memory cell of the neural memory unit is different than the thermal relationship between the primary memory cell and at least one other secondary memory cell of the plurality of secondary memory cells.   
     
     
         10 . An apparatus, comprising:
 a neural memory unit having a primary memory cell and a plurality of secondary memory cells, the plurality of secondary memory cells thermally coupled with the primary memory cell; and   a controller associated with the neural memory unit and configured to cause the apparatus to:
 select at least one memory cell of the neural memory unit for a read operation; 
 bias one or more word lines coupled with the neural memory unit based at least in part on selecting the at least one memory cell; 
 detect one or more signals generated on one or more digit lines coupled with the neural memory unit based at least in part on biasing the one or more word lines; and 
 determine an analog value stored by the neural memory unit based at least in part on detecting the one or more signals generated on the one or more digit lines. 
   
     
     
         11 . The apparatus of  claim 10 , wherein the controller is further configured to cause the apparatus to:
 detect a leakage current associated with at least one digit line of the one or more digit lines, wherein detecting the one or more signals is based at least in part on detecting the leakage current.   
     
     
         12 . The apparatus of  claim 11 , wherein the controller is further configured to cause the apparatus to:
 bias one or more unselected word lines with a voltage during the read operation, wherein detecting the leakage current associated with each digit line is based at least in part on biasing the one or more unselected word lines.   
     
     
         13 . The apparatus of  claim 10 , wherein the controller is further configured to cause the apparatus to:
 determine a weight value for each signal generated on each digit line of the one or more digit lines; and   combine the determined weight values for each signal generated on each digit line, wherein determining the analog value is based at least in part on combining the determined weight values.   
     
     
         14 . The apparatus of  claim 10 , wherein the controller is further configured to cause the apparatus to:
 precharge the one or more digit lines during the read operation, wherein detecting the one or more signals is based at least in part on precharging the one or more digit lines.   
     
     
         15 . The apparatus of  claim 14 , wherein the controller configured to cause the apparatus to precharge the one or more digit lines is further configured to cause the apparatus to:
 precharge a first digit line of the one or more digit lines during the read operation, wherein the first digit line is coupled with at least a first secondary memory cell;   precharge a second digit line of the one or more digit lines during the read operation, wherein the second digit line is coupled with the primary memory cell and more than one secondary memory cell; and   precharge a third digit line of the one or more digit lines during the read operation, wherein the third digit line is coupled with at least a second secondary memory cell, and wherein precharging the one or more digit lines is based at least in part on precharging the first digit line, the second digit line, and the third digit line.   
     
     
         16 . The apparatus of  claim 10 , wherein the controller is further configured to cause the apparatus to:
 bias a first word line of the one or more word lines during the read operation, wherein the first word line is coupled with at least a first secondary memory cell;   bias a second word line of the one or more word lines during the read operation, wherein the second word line is coupled with the primary memory cell and more than one secondary memory cell; and   bias a third word line of the one or more word lines during the read operation, wherein the third word line is coupled with at least a second secondary memory cell, and wherein biasing the one or more word lines is based at least in part on biasing the first word line, the second word line, and the third word line.   
     
     
         17 . The apparatus of  claim 10 , wherein:
 each secondary memory cell is thermally coupled with the primary memory cell according to a thermal relationship; and   the thermal relationship between the primary memory cell and a first secondary memory cell of the neural memory unit is different than the thermal relationship between the primary memory cell and at least one other secondary memory cell of the plurality of secondary memory cells.   
     
     
         18 . A method, comprising:
 selecting at least one memory cell of a neural memory unit for a read operation, the neural memory unit comprising a primary memory cell and a plurality of secondary memory cells thermally coupled with the primary memory cell;   biasing a first set of access lines coupled with the neural memory unit to a first voltage based at least in part on selecting the at least one memory cell;   biasing a second set of access lines to a second voltage different from the first voltage based at least in part on selecting the at least one memory cell;   detecting one or more signals generated on a set of digit lines coupled with the neural memory unit based at least in part on biasing the first set of access lines and biasing the second set of access lines; and   determining an analog value stored by the neural memory unit based at least in part on detecting the one or more signals generated on the set of digit lines.   
     
     
         19 . The method of  claim 18 , wherein detecting the one or more signals generated on the set of digit lines comprises:
 detecting a respective signal corresponding to each digit line of the set of digit lines, wherein determining the analog value is based at least in part on a sum of the respective signals.   
     
     
         20 . The method of  claim 18 , further comprising:
 precharging the first set of access lines and the second set of access lines during the read operation, wherein detecting the one or more signals is based at least in part on precharging the first set of access lines and the second set of access lines.   
     
     
         21 . The method of  claim 18 , wherein a first thermal relationship between the primary memory cell and a first secondary memory cell of the neural memory unit is different than a second thermal relationship between the primary memory cell and a second secondary memory cell of the neural memory unit based at least in part on the plurality of secondary memory cells being thermally coupled with the primary memory cell.