Performing logical operations using sensing circuitry

Abstract

The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.

21 . An apparatus, comprising:
 an array of memory cells; and   sensing circuitry coupled to the array of memory cells via a pair of complementary sense lines, wherein the sensing circuitry comprises:
 a sense amplifier coupled to the pair of complementary sense lines; and 
 a compute component selectively coupled to the sense amplifier via a first pass transistor and a second pass transistor, wherein the compute component comprises:
 a first transistor, a second transistor, a third transistor, and a fourth transistor; and 
 a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor, 
 wherein a first source/drain of the first transistor is directly coupled to a first source/drain of the first pass transistor, a first source/drain of the second transistor is directly coupled to a first source/drain of the second pass transistor, a second source/drain of the first transistor is directly coupled to a first source/drain of the first pull-down transistor, and a second source/drain of the second transistor is directly coupled to a first source/drain of the second pull-down transistor, and 
 wherein a first source/drain of the third transistor is directly coupled to the first source/drain of the first pass transistor, a first source/drain of the fourth transistor is directly coupled to the first source drain of the second pass transistor, a second source/drain of the third transistor is directly coupled to a first source/drain of the third pull-down transistor, and a second source/drain of the fourth transistor is directly coupled to a first source/drain of the fourth pull-down transistor. 
 
   
     
     
         22 . The apparatus of  claim 21 , wherein the first and second pass transistors of a same type, and
 wherein the first and second pass transistors are enabled via different control signals.   
     
     
         23 . The apparatus of  claim 21 , wherein a first source/drain of the first pass transistor is directly coupled to a first input node of the sense amplifier and a second source/drain of the first pass transistor is directly coupled to a first input node of the compute component, and
 wherein a first source/drain of the second pass transistor is directly coupled to a second input node of the sense amplifier and a second source/drain of the second pass transistor is directly coupled to a second input node of the compute component.   
     
     
         24 . The apparatus of  claim 21 , wherein the sense amplifier comprises a primary latch comprising a cross-coupled latch and equilibrate circuitry configured to equilibrate the pair of complementary sense lines. 
     
     
         25 . The apparatus of  claim 24 , wherein the equilibrate circuitry comprises:
 a first equilibrate transistor coupled between the pair of complementary sense lines;   a first source/drain of a second equilibrate transistor coupled to a first one of the pair of complementary sense lines;   a first source/drain of a third equilibrate transistor coupled to a second one of the pair of complementary sense lines;   a second source/drain of the second equilibrate transistor coupled to a second source/drain of a third equilibrate transistor; and   a gate of the first equilibrate transistor coupled to a gate of the second equilibrate transistor and to a gate of the third equilibrate transistor.   
     
     
         26 . The apparatus of  claim 21 , wherein transistors of the sensing circuitry are formed on pitch with memory cells of the array. 
     
     
         27 . The apparatus of  claim 21 , further comprising shift circuitry configured to selectively couple the pair of complementary sense lines between the array and the sensing circuitry. 
     
     
         28 . An apparatus, comprising:
 an array of memory cells; and   sensing circuitry coupled to the array of memory cells via a pair of complementary sense lines of the array, wherein the sensing circuitry comprises
 a first primary latch coupled to the pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines of the array via a first transistor and a second transistor; 
 a first secondary latch selectively coupled to the pair of complementary sense lines and to the first primary latch; 
 a second primary latch coupled to the pair of adjacent complementary sense lines and selectively coupled to the pair of complementary sense lines via the first pass transistor and the second pass transistor; and 
 a second secondary latch selectively coupled to the pair of adjacent complementary sense lines and to the second primary latch, 
   wherein the sensing circuitry is configured to shift a data value between the first primary latch and the second secondary latch via activation of the first pass transistor and the second pass transistor.   
     
     
         29 . The apparatus of  claim 28 , wherein the sensing circuitry comprises a sense amplifier comprising the primary latch and a compute component comprising the secondary latch. 
     
     
         30 . The apparatus of  claim 28 , wherein the sensing circuitry is further configured to:
 shift the data value without transferring the data value to circuitry external to the array or the sensing circuitry; and   shift the data value without activating a row line of the array.   
     
     
         31 . The apparatus of  claim 28 , wherein the first primary latch is selectively coupled to the first secondary latch via a first pass transistor and a second pass transistor, and
 wherein the second primary latch is selectively coupled to the second secondary latch via a third pass transistor and a fourth pass transistor.   
     
     
         32 . The apparatus of  claim 28 , wherein the sensing circuitry is further configured to:
 connect complementary nodes of the first secondary latch to the pair of complementary sense lines;   provide a complement of the data value from the first secondary latch to the pair of complementary sense lines; and   sense the complement of the data value from the pair of complementary sense lines to the first primary latch.   
     
     
         33 . The apparatus of  claim 28 , wherein the sensing circuitry is further configured to receive the data value or a complement of the data value into the first secondary latch. 
     
     
         34 . A method for data shifting, comprising:
 connecting, via activation of a first pair of shift transistors of sensing circuitry, a compute component of the sensing circuitry coupled to a pair of complementary sense lines of an array of memory cells to a first pair of adjacent complementary sense lines of the array,   wherein the compute component is coupled to a first sense amplifier of the sensing circuitry coupled to the pair of complementary sense lines via a first pass transistor and a second pass transistor, and   wherein the compute component comprises:
 a first transistor having a first source/drain of directly coupled to a first source/drain of the first pass transistor and a second source/drain directly coupled to a source/drain of a first pull-down transistor; 
 a second transistor having a first source/drain directly coupled to a first source/drain of the second pass transistor and a second source/drain directly coupled to a source/drain of a second pull-down transistor; 
 a third transistor having wherein a first source/drain directly coupled to the first source/drain of the first pass transistor and a second source/drain directly coupled to a source/drain of a third pull-down transistor; and 
 a fourth transistor having a first source/drain directly coupled to the first source drain of the second pass transistor and a second source/drain directly coupled to a source/drain of a fourth pull-down transistor; 
   storing a first data value from the compute component to a second sense amplifier of the sensing circuitry coupled to the first pair of adjacent complementary sense lines;   connecting, via activation of a second pair of shift transistors of the sensing circuitry, the compute component to a second pair of adjacent complementary sense lines of the array; and   loading a second data value from the second pair of adjacent complementary sense lines into the compute component.   
     
     
         35 . The method of  claim 34 , wherein loading the second data value comprises connecting the compute component to the second pair of complementary sense lines through a pass transistor. 
     
     
         36 . The method of  claim 34 , wherein storing the first data value comprises equilibrating the first pair of adjacent complementary sense lines. 
     
     
         37 . The method of  claim 34 , further comprising, subsequent to storing the first data value, isolating the second sense amplifier from the second pair of adjacent complementary sense lines. 
     
     
         38 . The method of  claim 34 , wherein connecting the compute component to the first pair of adjacent complementary sense lines comprises applying a shift control signal to respective gates of the first pair of shift transistors. 
     
     
         39 . The method of  claim 38 , wherein connecting the compute component to the second pair of adjacent complementary sense lines comprises applying the shift control signal to respective gates of the second pair of shift transistors. 
     
     
         40 . The method of  claim 34 , further comprising, prior to loading the second data value, performing a sensing operation on a memory cell coupled to the second pair of adjacent complementary sense lines to store the second data value to a third sense amplifier coupled to the second pair of adjacent complementary sense lines.