Integrated circuit with scribe lane patterns for defect reduction

Abstract

An integrated circuit includes a circuit area, and first and second scribe line portions. The first scribe line portion borders a first side of the circuit area, and the second scribe line portion borders a different second side of the circuit area. A plurality of dummy metal structures are located in the first and second scribe line portions, each of the dummy metal structures being located about at a lattice point of a same two-dimensional grid.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a plurality of dummy metal structures, each dummy metal structure located about at a lattice point of a same two-dimensional grid; and   a die having a circuit formed thereupon in a circuit area, the circuit area located within the two-dimensional grid such that the circuit area is bordered on a first side by a first wafer scribe lane portion including a first subset of the dummy metal structures, and the circuit area is bordered on a second side by a second wafer scribe lane portion including a second subset of the dummy metal structures.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the two-dimensional grid is a hexagonal grid. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the two-dimensional grid is a rectilinear grid. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the two-dimensional grid is a skewed grid. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the dummy metal structures are arranged such that when dummy metal structures of the first subset are translated along an axis of the die, each dummy metal structure of the first subset directly overlies a corresponding dummy metal structure of the second subset. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the first and second subsets of dummy pattern structures are located in orthogonal scribe lanes. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the circuit area is surrounded on all sides by the dummy metal structures. 
     
     
         8 . The integrated circuit of  claim 1 , wherein the dummy metal structures in the first subset are larger than the dummy metal structures in the second subset. 
     
     
         9 . The integrated circuit of  claim 1 , wherein the dummy metal structures comprise bowtie structures or chevrons. 
     
     
         10 . An integrated circuit, comprising:
 a circuit area;   a first scribe line portion bordering a first side of the circuit area;   a second scribe line portion bordering a different second side of the circuit area;   a plurality of dummy metal structures located in the first and second scribe line portions, each dummy metal structure located about at a lattice point of a same two-dimensional grid.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the first and second scribe line portions are on opposite sides of the circuit area. 
     
     
         12 . The integrated circuit of  claim 10 , wherein the first and second scribe line portions are on adjacent sides of the circuit area. 
     
     
         13 . The integrated circuit of  claim 10 , wherein the dummy metal structures comprise bowtie structures. 
     
     
         14 . The integrated circuit of  claim 10 , wherein the dummy metal structures in the first scribe line portion have an area about 0.16 square microns less than the dummy metal structures in the second scribe line portion. 
     
     
         15 . The integrated circuit of  claim 10 , further comprising third and fourth scribe line portions bordering respective third and fourth sides of the circuit area, an additional plurality of dummy metal structures located in the third and fourth scribe line portions, each dummy metal structure of the additional plurality located about at a lattice point of the same two-dimensional grid. 
     
     
         16 . The integrated circuit of  claim 10 , wherein the dummy metal structures are arranged such that when dummy metal structures in the first scribe line portion are translated along an axis of the die, each dummy metal structure in the first scribe line portion overlies a corresponding dummy metal structure in the second of the second scribe line portion. 
     
     
         17 . The integrated circuit of  claim 10 , wherein the dummy metal structures in the first scribe line portion are larger than the dummy metal structures in the second scribe line portion. 
     
     
         18 . The integrated circuit of  claim 10 , wherein the two-dimensional grid is a rectilinear grid.