High voltage pmos (hvpmos) transistor with a composite drift region and manufacture method thereof

Abstract

In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.

1 .- 15 . (canceled) 
     
     
         16 . A method of making a high voltage MOS (HVMOS) transistor, the method comprising:
 a) providing a semiconductor layer;   b) implanting first doping type dopants of different doping concentrations in said semiconductor layer along a first direction extending from a gate contact to a drain contact of said HVMOS transistor;   c) dispersing said implanted first doping type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along said first direction;   d) forming a gate dielectric layer on said semiconductor layer; and   e) forming a composite oxide layer on said composite drift region, wherein said composite oxide layer comprises at least two adjacent single oxide layers having a same thickness or an increasing thickness along said first direction.   
     
     
         17 . The method of  claim 16 , wherein said forming said composite drift region comprises:
 a) implanting and dispersing, at a first time, first doping type dopants in said semiconductor layer to form a first drift region having a lowest doping concentration and a lowest junction depth; and   b) implanting and dispersing, beginning from a side wall of said first drift region and from at a second time to an n th  time in sequence, first doping type dopants of increasing doping concentrations along said first direction, to form adjacent second to n th  drift regions having progressively increasing doping concentrations and junction depths, wherein n is an integer of at least two.   
     
     
         18 . The method of  claim 17 , further comprising forming a composite oxide layer by depositing oxide material on said composite drift region at least twice to form at least two adjacent single oxide layers along said first direction. 
     
     
         19 . The method of  claim 18 , wherein:
 a) forming said composite oxide layer occurs after forming said first drift region; and   b) forming said composite oxide layer occurs before or after forming said second drift region through said n th  drift region.   
     
     
         20 . The method of  claim 18 , wherein said at least two adjacent single oxide layers comprises a same thickness or an increasing thickness along said first direction. 
     
     
         21 . The method of  claim 18 , further comprising:
 a) forming said gate contact by depositing polysilicon on a gate dielectric layer of said high voltage MOS transistor and a portion of said composite oxide layer that is on said first drift region;   b) forming a first doping type source contact and a second doping type body contact by implanting first doping type dopants and second doping type dopants separately in a portion of said semiconductor layer that is outside of said composite drift region; and   c) forming said drain contact by implanting first doping type dopants in a portion of said n th  drift region adjacent to said composite oxide layer.   
     
     
         22 . The method of  claim 16 , wherein providing a semiconductor layer comprises providing a substrate having said first doping type, and forming a deep well having a second doping type in said substrate, said composite drift region is located in said deep well.