Semiconductor device structure

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a multilayer stack over the base. The semiconductor device structure includes a gate stack over the substrate and wrapping around the multilayer stack. The semiconductor device structure includes a dielectric layer over the base and covering a first sidewall of the multilayer stack. A first upper surface of the dielectric layer is lower than a second upper surface of the multilayer stack. The semiconductor device structure includes a stressor over a second sidewall of the multilayer stack. The first sidewall is opposite to the second sidewall.

What is claimed is: 
     
         1 . A semiconductor device structure, comprising:
 a substrate having a base and a multilayer stack over the base;   a gate stack over the substrate and wrapping around the multilayer stack;   a dielectric layer over the base and covering a first sidewall of the multilayer stack, wherein a first upper surface of the dielectric layer is lower than a second upper surface of the multilayer stack; and   a stressor over a second sidewall of the multilayer stack, wherein the first sidewall is opposite to the second sidewall.   
     
     
         2 . The semiconductor device structure as claimed in  claim 1 , wherein the second upper surface of the multilayer stack is lower than a third upper surface of the stressor. 
     
     
         3 . The semiconductor device structure as claimed in  claim 1 , wherein the first upper surface of the dielectric layer is a concave surface. 
     
     
         4 . The semiconductor device structure as claimed in  claim 1 , further comprising:
 an etch stop layer covering the first sidewall of the multilayer stack and between the dielectric layer and the multilayer stack.   
     
     
         5 . The semiconductor device structure as claimed in  claim 4 , wherein the etch stop layer continuously covers the first sidewall of the multilayer stack and a third sidewall of the gate stack. 
     
     
         6 . The semiconductor device structure as claimed in  claim 1 , further comprising:
 a dummy contact structure over the dielectric layer.   
     
     
         7 . The semiconductor device structure as claimed in  claim 6 , wherein the dummy contact structure partially extends into the dielectric layer. 
     
     
         8 . The semiconductor device structure as claimed in  claim 6 , wherein a bottom surface of the dummy contact structure is lower than the second upper surface of the multilayer stack. 
     
     
         9 . The semiconductor device structure as claimed in  claim 8 , wherein the bottom surface of the dummy contact structure is a convex surface. 
     
     
         10 . The semiconductor device structure as claimed in  claim 6 , further comprising:
 an etch stop layer covering the first sidewall of the multilayer stack and between the dielectric layer and the multilayer stack and between the dummy contact structure and the multilayer stack.   
     
     
         11 . A semiconductor device structure, comprising:
 a substrate having a base, a first multilayer stack, and a second multilayer stack over the base, wherein the first multilayer stack and the second multilayer stack are separated by a gap;   a first gate stack and a second gate stack over the substrate, wherein the first gate stack wraps around the first multilayer stack, and the second gate stack wraps around the second multilayer stack;   a dielectric layer in the gap and covering a first sidewall of the first multilayer stack and a second sidewall of the second multilayer stack, wherein the first sidewall and the second sidewall face each other; and   a first stressor over a third sidewall of the first multilayer stack, wherein the first sidewall is opposite to the third sidewall.   
     
     
         12 . The semiconductor device structure as claimed in  claim 11 , further comprising:
 a second stressor over a fourth sidewall of the second multilayer stack, wherein the second sidewall is opposite to the fourth sidewall.   
     
     
         13 . The semiconductor device structure as claimed in  claim 11 , further comprising:
 an etch stop layer continuously covering the first sidewall of the first multilayer stack and the second sidewall of the second multilayer stack and between the dielectric layer and the base.   
     
     
         14 . The semiconductor device structure as claimed in  claim 13 , wherein the etch stop layer has a U-like shape. 
     
     
         15 . The semiconductor device structure as claimed in  claim 13 , further comprising:
 a bottom spacer between the dielectric layer and the base of the substrate, wherein the etch stop layer is between the dielectric layer and the bottom spacer.   
     
     
         16 . A semiconductor device structure, comprising:
 a substrate having a base and a first multilayer stack over the base;   a first gate stack over the substrate, wherein the first gate stack wraps around the first multilayer stack;   a first spacer over a first sidewall of the first gate stack, wherein a second sidewall of the first spacer is substantially level with a third sidewall of the first multilayer stack;   a dielectric layer over the base and covering the third sidewall; and   a stressor over a fourth sidewall of the first multilayer stack, wherein the third sidewall is opposite to the fourth sidewall.   
     
     
         17 . The semiconductor device structure as claimed in  claim 16 , wherein the stressor is in direct contact with the first multilayer stack. 
     
     
         18 . The semiconductor device structure as claimed in  claim 16 , further comprising:
 an etch stop layer continuously covering the second sidewall and the third sidewall, wherein the etch stop layer is between the dielectric layer and the first multilayer stack.   
     
     
         19 . The semiconductor device structure as claimed in  claim 16 , wherein the substrate further has a second multilayer stack over the base, and the semiconductor device structure further comprises:
 a second gate stack over the substrate, wherein the second gate stack wraps around the second multilayer stack;   a second spacer over a fifth sidewall of the second gate stack, wherein a sixth sidewall of the second spacer is level with a seventh sidewall of the second multilayer stack, and the dielectric layer further covers the seventh sidewall; and   a second stressor over an eighth sidewall of the second multilayer stack, wherein the seventh sidewall is opposite to the eighth sidewall.   
     
     
         20 . The semiconductor device structure as claimed in  claim 19 , further comprising:
 a contact structure between the first gate stack and the second gate stack and between the first multilayer stack and the second multilayer stack, wherein the contact structure is over the dielectric layer.