US2021391344A1PendingUtilityA1

High-voltage transistor having shielding gate

Assignee: TOSHIBA MEMORY CORPPriority: Aug 19, 2004Filed: Aug 30, 2021Published: Dec 16, 2021
Est. expiryAug 19, 2024(expired)· nominal 20-yr term from priority
H10W 20/43H10D 89/10H10D 64/112H10D 64/111H10D 62/115G11C 16/0408G11C 16/08H01L 27/11521H01L 27/105H01L 29/404H01L 23/528H01L 27/11526H01L 27/11286H01L 27/115H01L 29/0649H01L 27/11524H01L 29/402H01L 27/0207H10B 41/30H10B 41/40H10B 20/60H10B 69/00H10B 41/35
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Claims

Abstract

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

Claims

exact text as granted — not AI-modified
1 - 4 . (canceled) 
     
     
         5 . A semiconductor device comprising:
 first, second, third, and fourth high-voltage transistors on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent to each other in a gate-width direction, the third and fourth high-voltage transistors being adjacent to each other in the gate-width direction, the first and third high-voltage transistors being adjacent to each other in a gate-length direction, and the second and fourth high-voltage transistors being adjacent to each other in the gate-length direction,
 wherein the first high-voltage transistor includes a first gate electrode and a first gate electrode contact on the first gate electrode, 
 the second high-voltage transistor includes a second gate electrode and a second gate electrode contact on the second gate electrode, 
 the third high-voltage transistor includes a third gate electrode and a third gate electrode contact on the third gate electrode, and 
 the fourth high-voltage transistor includes a fourth gate electrode and a fourth gate electrode contact on the fourth gate electrode; and 
   a shielding gate provided on an element isolation region such that the shielding gate extends across a first portion of the element isolation region between the first and third high-voltage transistors and a second portion of the element isolation region between the second and fourth high-voltage transistors.

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