Warpage control for microelectronics packages

Abstract

Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.

What is claimed is: 
     
         1 . A method of fabricating a microelectronic device, comprising:
 attaching a microelectronics die to a top surface of a coreless substrate;   attaching a stiffener to a bottom surface of the coreless substrate using an adhesive;   attaching solder to the bottom surface of the coreless substrate; and   attaching the microelectronics die, coreless substrate, and stiffener to a motherboard using the solder, wherein the stiffener is positioned between the motherboard and the coreless substrate.   
     
     
         2 . The method of  claim 1 , further comprising selecting a thickness of the stiffener to be approximately equal to a thickness of the microelectronics die. 
     
     
         3 . The method of  claim 1 , further comprising selecting a coefficient of thermal expansion (CTE) of the stiffener to approximately equal a CTE of the microelectronics die. 
     
     
         4 . The method of  claim 1 , further comprising selecting the stiffener to be an insulating stiffener. 
     
     
         5 . The method of  claim 1 , further comprising selecting the stiffener to be a metallic stiffener. 
     
     
         6 . A method of fabricating a microelectronic device, comprising:
 providing a glass base;   forming copper pads on a top surface of the glass base;   forming a build-up layer on the top surface of the glass base and over the copper pads;   forming openings in the glass base aligned with the copper pads;   providing copper pillar segments in one or more interior openings of the glass base;   attaching a microelectronics die to the build-up layer;   depositing solder in one or more outer openings in the glass base; and   attaching the build-up layer to a motherboard using the solder such that the glass base is positioned between the motherboard and the build-up layer.   
     
     
         7 . The method of  claim 6 , wherein a height of each of the copper pillar segments is approximately equal to a thickness of the glass base. 
     
     
         8 . The method of  claim 6 , wherein a thickness of the glass base is approximately equal to a thickness of the microelectronics die. 
     
     
         9 . The method of  claim 6 , wherein a coefficient of thermal expansion (CTE) of the glass base approximately matches a CTE of the microelectronics die. 
     
     
         10 . A method of fabricating a microelectronic device, comprising:
 attaching a stiffener to a bottom surface of a coreless substrate using an adhesive, the coreless substrate comprising a microelectronics die attached to a top surface of the coreless substrate;   attaching solder to the bottom surface of the coreless substrate; and   attaching the microelectronics die, coreless substrate, and stiffener to a motherboard using the solder, wherein the stiffener is positioned between the motherboard and the coreless substrate.   
     
     
         11 . The method of  claim 10 , further comprising selecting a thickness of the stiffener to be approximately equal to a thickness of the microelectronics die. 
     
     
         12 . The method of  claim 10 , further comprising selecting a coefficient of thermal expansion (CTE) of the stiffener to approximately equal a CTE of the microelectronics die. 
     
     
         13 . The method of  claim 10 , further comprising selecting the stiffener to be an insulating stiffener. 
     
     
         14 . The method of  claim 10 , further comprising selecting the stiffener to be a metallic stiffener. 
     
     
         15 . A method of fabricating a microelectronic device, comprising:
 forming copper pads on a top surface of a glass base;   forming a build-up layer on the top surface of the glass base and over the copper pads;   forming openings in the glass base aligned with the copper pads;   providing copper pillar segments in one or more interior openings of the glass base;   attaching a microelectronics die to the build-up layer;   depositing solder in one or more outer openings in the glass base; and   attaching the build-up layer to a motherboard using the solder such that the glass base is positioned between the motherboard and the build-up layer.   
     
     
         16 . The method of  claim 15 , wherein a height of each of the copper pillar segments is approximately equal to a thickness of the glass base. 
     
     
         17 . The method of  claim 15 , wherein a thickness of the glass base is approximately equal to a thickness of the microelectronics die. 
     
     
         18 . The method of  claim 15 , wherein a coefficient of thermal expansion (CTE) of the glass base approximately matches a CTE of the microelectronics die.