US2021385016A1PendingUtilityA1
Polar coding systems, procedures, and signaling
Est. expiryMar 22, 2037(~10.7 yrs left)· nominal 20-yr term from priority
H04L 1/0057H03M 13/6368H03M 13/2792H03M 13/2778H03M 13/13H03M 13/05H04L 1/0071H04L 1/0067H04L 1/0041H03M 13/6362H03M 13/6356H03M 13/6306H03M 13/618H03M 13/2906H03M 13/27H03M 13/6522H04L 1/0072H04L 1/0061
70
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Claims
Abstract
Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A wireless transmit/receive unit (WTRU) configured to:
generate a plurality of polar encoded bits using polar encoding, wherein the plurality of polar encoded bits is generated using a mother code length; divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner, wherein a size of each sub-block is a ratio of the mother code length and a number of the sub-blocks; apply sub-block wise interleaving to the sub-blocks using an interleaver pattern, wherein sub-blocks associated with a subset of the sub-blocks are interleaved, and sub-blocks associated with another subset of the sub-blocks are not interleaved wherein the sub-block wise interleaving comprises applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks; and concatenate bits from each of the interleaved sub-blocks, wherein bits associated with each of the interleaved sub-blocks are sequentially concatenated.
2 . The WTRU of claim 1 , wherein the subset of sub-blocks that are interleaved and the subset of sub-blocks that are not interleaved are consecutive and non-overlapping.
3 . The WTRU of claim 1 , wherein a first subset of sub-blocks that are interleaved are middle sub-blocks of the sub-blocks, and wherein a second subset of sub-blocks that are not interleaved are an even number of sub-blocks, and wherein the second subset of sub-blocks comprises an equal number of sub-blocks on each side of the first subset of sub-blocks.
4 . The WTRU of claim 3 , wherein a third subset of sub-blocks that is interleaved is adjacent to the second subset of sub-blocks.
5 . The WTRU of claim 4 , wherein a fourth subset of sub-blocks that is not interleaved comprises sub-blocks other than the first subset of sub-blocks, the second subset of sub-blocks, and the third subset of sub-blocks, and wherein the fourth subset of sub-blocks are adjacent to the third subset of sub-blocks.
6 . The WTRU of claim 1 , wherein the WTRU is further configured to store the interleaved bits associated with the interleaved sub-blocks in a circular buffer.
7 . The WTRU of claim 6 , wherein the WTRU is further configured to select a plurality of bits for transmission from the interleaved bits contiguously stored in the circular buffer, wherein the plurality of bits is selected based on a rate matching scheme, wherein the rate matching scheme is determined based on the mother code length, a rate matching output size, and a code rate, and wherein the rate matching scheme is one of a repetition scheme, a puncturing scheme, or a shortening scheme.
8 . The WTRU of claim 7 , wherein the rate matching scheme is a repetition scheme when rate matching output size is greater than the mother code length, and wherein the rate matching scheme is a shortening scheme or a puncturing scheme when rate matching output size is less than the mother code length, wherein selection between the shortening scheme and the puncturing scheme is based on a code rate.
9 . The WTRU of claim 1 , wherein the interleaver pattern is given by d 1 ( ) in the following equation:
I
s
(
i
)
=
B
·
d
1
(
i
B
)
+
d
2
(
mod
(
i
,
B
)
)
10 . The WTRU of claim 1 , wherein the sub-block wise interleaving results in the following pattern: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7, wherein the subset of sub-blocks that are interleaved comprises d 1 [2] through d 1 [5], and the subset of sub-blocks that are not interleaved comprises d 1 [0] through d 1 [1], and d 1 [6] through d 1 [7].
11 . The WTRU of claim 1 , wherein the concatenated bits are interleaved as a result of the sub-block wise interleaving.
12 . An interleaving method comprising:
generating a plurality of polar encoded bits using polar encoding, wherein the plurality of polar encoded bits is generated using a mother code length; dividing the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner, wherein a size of each sub-block is a ratio of the mother code length and a number of the sub-blocks; applying sub-block wise interleaving to the sub-blocks using an interleaver pattern, wherein sub-blocks associated with a subset of the sub-blocks are interleaved, and sub-blocks associated with another subset of the sub-blocks are not interleaved wherein the sub-block wise interleaving comprises applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks; and concatenating bits from each of the interleaved sub-blocks, wherein bits associated with each of the interleaved sub-blocks are sequentially concatenated.
13 . The WTRU of claim 12 , wherein the subset of sub-blocks that are interleaved and the subset of sub-blocks that are not interleaved are consecutive and non-overlapping.
14 . The WTRU of claim 12 , wherein a first subset of sub-blocks that are interleaved are middle sub-blocks of the sub-blocks, and wherein a second subset of sub-blocks that are not interleaved are an even number of sub-blocks, and wherein the second subset of sub-blocks comprises an equal number of sub-blocks on each side of the first subset of sub-blocks.
15 . The WTRU of claim 14 , wherein a third subset of sub-blocks that is interleaved is adjacent to the second subset of sub-blocks.
16 . The WTRU of claim 15 , wherein a fourth subset of sub-blocks that is not interleaved comprises sub-blocks other than the first subset of sub-blocks, the second subset of sub-blocks, and the third subset of sub-blocks, and wherein the fourth subset of sub-blocks are adjacent to the third subset of sub-blocks.
17 . The WTRU of claim 12 , comprising storing the interleaved bits associated with the interleaved sub-blocks in a circular buffer.
18 . The WTRU of claim 17 , comprising selecting a plurality of bits for transmission from the interleaved bits contiguously stored in the circular buffer, wherein the plurality of bits is selected based on a rate matching scheme, wherein the rate matching scheme is determined based on the mother code length, a rate matching output size, and a code rate, and wherein the rate matching scheme is one of a repetition scheme, a puncturing scheme, or a shortening scheme.
19 . The WTRU of claim 18 , wherein the rate matching scheme is a repetition scheme when rate matching output size is greater than the mother code length, and wherein the rate matching scheme is a shortening scheme or a puncturing scheme when rate matching output size is less than the mother code length, wherein selection between the shortening scheme and the puncturing scheme is based on a code rate.
20 . The WTRU of claim 12 , wherein the interleaver pattern is given by d 1 ( ) in the following equation:
I
s
(
i
)
=
B
·
d
1
(
i
B
)
+
d
2
(
mod
(
i
,
B
)
)
21 . The WTRU of claim 12 , wherein the sub-block wise interleaving results in the following pattern: d 1 [0]=0, d 1 [1]=1, d 1 [2]=2, d 1 [3]=4, d 1 [4]=3, d 1 [5]=5, d 1 [6]=6, d 1 [7]=7, wherein the subset of sub-blocks that are interleaved comprises d 1 [2] through d 1 [5], and the subset of sub-blocks that are not interleaved comprises d 1 [0] through d 1 [1], and d 1 [6] through d 1 [7].
22 . The WTRU of claim 12 , wherein the concatenated bits are interleaved as a result of the sub-block wise interleaving.Join the waitlist — get patent alerts
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