Semiconductor device, electronic component, and electronic device

Abstract

A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

1 . A semiconductor device comprising:
 a cell array including a first memory cell and a second memory cell; and   a first wiring, a second wiring, and a third wiring,   wherein the first memory cell includes a first transistor and a first capacitor,   wherein the second memory cell includes a second transistor and a second capacitor,   wherein one electrode of the first capacitor is electrically connected to one of a source and a drain of the first transistor,   wherein one electrode of the second capacitor is electrically connected to one of a source and a drain of the second transistor,   wherein the first wiring is electrically connected to a gate of the first transistor,   wherein the second wiring is electrically connected to a gate of the second transistor, and   wherein the third wiring is electrically connected to the other of the source and the drain of the first transistor and to the other of the source and the drain of the second transistor.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein channels of the first transistor and the second transistor are formed in one semiconductor layer. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the one semiconductor layer is oxide semiconductor. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein a ground potential is supplied to the other electrodes of the first capacitor and the second capacitor. 
     
     
         5 . A semiconductor device comprising:
 a cell array including a first memory cell and a second memory cell; and   a first wiring, a second wiring, and a third wiring,   wherein the first memory cell includes a first transistor and a first capacitor,   wherein the second memory cell includes a second transistor and a second capacitor,   wherein one electrode of the first capacitor is electrically connected to one of a source and a drain of the first transistor,   wherein one electrode of the second capacitor is electrically connected to one of a source and a drain of the second transistor,   wherein the first wiring is electrically connected to a gate of the first transistor,   wherein the second wiring is electrically connected to a gate of the second transistor,   wherein the third wiring is electrically connected to the other of the source and the drain of the first transistor and to the other of the source and the drain of the second transistor, and   wherein each of the first transistor and the second transistor includes a back gate.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein channels of the first transistor and the second transistor are formed in one semiconductor layer. 
     
     
         7 . The semiconductor device according to  claim 6 , wherein the one semiconductor layer is oxide semiconductor. 
     
     
         8 . The semiconductor device according to  claim 5 , wherein a ground potential is supplied to the other electrodes of the first capacitor and the second capacitor.