Semiconductor device with adjustment layers and method for fabricating the same

Abstract

The present application discloses a semiconductor device with adjustment layers and a method for fabricating the semiconductor device with the adjustment layers. The semiconductor device includes a substrate, an interconnection structure positioned on the substrate, a contact positioned penetrating the interconnection structure, and two adjustment layers positioned on sidewalls of the contact.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   an interconnection structure positioned on the substrate;   a contact positioned penetrating the interconnection structure; and   two adjustment layers positioned on sidewalls of the contact.   
     
     
         2 . The semiconductor device of  claim 1 , wherein a thickness of the adjustment layers gradually decrease toward the substrate. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a thickness of top surfaces of the two adjustment layers is between about 1 angstrom and about 30 angstroms. 
     
     
         4 . The semiconductor device of  claim 1 , wherein an aspect ratio of the contact is between about 1:3 and about 1:15. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a contact barrier layer positioned between the interconnection structure and the contact and between the substrate and the contact, wherein the two adjustment layers are positioned between the contact and the contact barrier layer. 
     
     
         6 . The semiconductor device of  claim 5 , wherein a bottom segment of the contact barrier layer is positioned between the substrate and the contact, and bottom most points of the two adjustment layers contact the bottom portion of the contact barrier layer. 
     
     
         7 . The semiconductor device of  claim 5 , wherein a thickness of the contact barrier layer is between about 10 angstroms and about 15 angstroms. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the interconnection structure comprises a first liner layer positioned on the substrate, a first insulating layer positioned on the first liner layer, a second liner layer positioned on the first insulating layer, and a second insulating layer positioned on the second liner layer, and the contact positioned penetrating the second insulating layer, the second liner layer, the first insulating layer, and the first liner layer. 
     
     
         9 . The semiconductor device of  claim 8 , wherein bottom most points of the two adjustment layers are at a vertical level lower than a vertical level of the second liner layer. 
     
     
         10 . The semiconductor device of  claim 8 , wherein a dielectric constant of the first insulating layer is equal to or less than 3.0. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the first insulating layer is porous. 
     
     
         12 . The semiconductor device of  claim 11 , wherein a porosity of the first insulating layer is between about 15% and about 50%. 
     
     
         13 . The semiconductor device of  claim 8 , wherein the two adjustment layers are formed of metal oxide, metal nitride, or metal carbide. 
     
     
         14 . The semiconductor device of  claim 8 , wherein an angle between a top surface of the contact and one of the sidewalls of the contact is between about 83 degree and about 90 degree. 
     
     
         15 . A method for fabricating a semiconductor device, comprising:
 providing a substrate;   forming an interconnection structure on the substrate;   forming a contact opening penetrating the interconnection structure;   conformally forming a contact barrier layer in the contact opening;   conformally forming adjustment layers covering upper portions of the contact barrier layer; and   forming a contact in the contact opening.   
     
     
         16 . The method for fabricating the semiconductor device of  claim 15 , wherein the adjustment layers are formed of metal oxide, metal nitride, or metal carbide. 
     
     
         17 . The method for fabricating the semiconductor device of  claim 16 , wherein the step of forming the interconnection structure on the substrate comprises:
 forming a first liner layer on the substrate;   forming a first insulating layer on the first liner layer;   forming a second liner layer on the first insulating layer; and   forming a second insulating layer on the second liner layer;   wherein the contact opening is formed penetrating the second insulating layer, the second liner layer, the first insulating layer, and the first liner layer.   
     
     
         18 . The method for fabricating the semiconductor device of  claim 17 , wherein the step of forming the first insulating layer on the first liner layer comprises:
 forming a layer of energy-removable material on the first liner layer; and   performing an energy treatment to turn the layer of energy-removable material into the first insulating layer;   wherein a porosity of the first insulating layer is between about 15% and about 50%.   
     
     
         19 . The method for fabricating the semiconductor device of  claim 18 , wherein an energy source of the energy treatment is heat, light, or a combination thereof. 
     
     
         20 . The method for fabricating the semiconductor device of  claim 19 , wherein the layer of energy-removable material comprises a base material and a decomposable porogen material.