Methods and apparatus for reducing reliability degradation on an integrated circuit

Abstract

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 programmable logic circuitry that is configurable to implement a circuit design using a first configuration image, wherein the programmable logic circuitry is reconfigurable to implement the circuit design using a second configuration image that is different than the first configuration image in response to restarting the integrated circuit.   
     
     
         2 . The integrated circuit of  claim 1 , wherein:
 the first configuration image configures a first portion of the programmable logic circuitry as a quiet region and configures a second portion of the programmable logic circuitry as a toggling region; and   the second configuration image reconfigures the first portion of the programmable logic circuitry as the toggling region and reconfigures the second portion of the programmable logic circuitry as the quiet region.   
     
     
         3 . The integrated circuit of  claim 1 , wherein:
 the first configuration image configures a first portion of the programmable logic circuitry as a quiet region and configures a second portion of the programmable logic circuitry as an unused region; and   the second configuration image reconfigures the first portion of the programmable logic circuitry as the unused region and reconfigures the second portion of the programmable logic circuitry as the quiet region.   
     
     
         4 . The integrated circuit of  claim 1 , wherein:
 the first configuration image configures a first conductive routing path in the programmable logic circuitry to convey a first amount of current and configures a second conductive routing path in the programmable logic circuitry to convey a second amount of current that is less than half of the first amount of current; and   the second configuration image reconfigures the first conductive routing path in the programmable logic circuitry to convey the second amount of current and reconfigures the second conductive routing path in the programmable logic circuitry to convey the first amount of current.   
     
     
         5 . The integrated circuit of  claim 1 , wherein:
 the first configuration image is generated using a first random fitter seed and has a first usage coverage region on the integrated circuit; and   the second configuration image is generated using a second random fitter seed and has a second usage coverage region on the integrated circuit that is different than the first usage coverage region.   
     
     
         6 . The integrated circuit of  claim 5 , wherein the first configuration image has a first set of unused regions, and wherein the second configuration image has a second set of unused regions that is at least partially non-overlapping with the first set of unused regions. 
     
     
         7 . The integrated circuit of  claim 5 , wherein the first configuration image has a first set of quiet regions, and wherein the second configuration image has a second set of quiet regions that is at least partially non-overlapping with the first set of quiet regions. 
     
     
         8 . The integrated circuit of  claim 1 , wherein:
 the first configuration image is generated using a first random fitter seed to perform place and route; and   the second configuration image is generated using a second random fitter seed that is different than the first random fitter seed to perform place and route.   
     
     
         9 . The integrated circuit of  claim 8 , wherein the first configuration image has a first set of unused regions, and wherein the second configuration image has a second set of unused regions that is at least partially non-overlapping with the first set of unused regions. 
     
     
         10 . The integrated circuit of  claim 8 , wherein the first configuration image has a first set of quiet regions, and wherein the second configuration image has a second set of quiet regions that is at least partially non-overlapping with the first set of quiet regions. 
     
     
         11 . An integrated circuit, comprising:
 programmable logic circuitry that is configurable to implement a circuit design using a first configuration image generated using a first random fitter seed, wherein the programmable logic circuitry is reconfigurable to implement the circuit design using a second configuration image that is different than the first configuration image and that is generated using a second random fitter seed that is different than the first random fitter seed.   
     
     
         12 . The integrated circuit of  claim 11 , wherein:
 the first configuration image configures a first portion of the programmable logic circuitry as a quiet region and configures a second portion of the programmable logic circuitry as a toggling region; and   the second configuration image reconfigures the first portion of the programmable logic circuitry as the toggling region and reconfigures the second portion of the programmable logic circuitry as the quiet region.   
     
     
         13 . The integrated circuit of  claim 11 , wherein:
 the first configuration image configures a first portion of the programmable logic circuitry as a quiet region and configures a second portion of the programmable logic circuitry as an unused region; and   the second configuration image reconfigures the first portion of the programmable logic circuitry as the unused region and reconfigures the second portion of the programmable logic circuitry as the quiet region.   
     
     
         14 . The integrated circuit of  claim 11 , wherein:
 the first configuration image configures a first conductive routing path in the programmable logic circuitry to convey a first amount of current and configures a second conductive routing path in the programmable logic circuitry to convey a second amount of current that is less than half of the first amount of current; and   the second configuration image reconfigures the first conductive routing path in the programmable logic circuitry to convey the second amount of current and reconfigures the second conductive routing path in the programmable logic circuitry to convey the first amount of current.   
     
     
         15 . The integrated circuit of  claim 11 , wherein:
 the first configuration image has a first usage coverage region on the integrated circuit; and   the second configuration image has a second usage coverage region on the integrated circuit that is different than the first usage coverage region.   
     
     
         16 . The integrated circuit of  claim 11 , wherein the first configuration image has a first set of unused regions, and wherein the second configuration image has a second set of unused regions that is at least partially non-overlapping with the first set of unused regions. 
     
     
         17 . The integrated circuit of  claim 11 , wherein the first configuration image has a first set of quiet regions, and wherein the second configuration image has a second set of quiet regions that is at least partially non-overlapping with the first set of quiet regions. 
     
     
         18 . The integrated circuit of  claim 11 , wherein:
 the first configuration image is generated using the first random fitter seed to perform place and route; and   the second configuration image is generated using the second random fitter seed to perform place and route.   
     
     
         19 . An integrated circuit, comprising:
 programmable logic circuitry that is configurable to implement a circuit design using a first configuration image, wherein placement of the first configuration image in the programmable logic circuitry is based on a first random fitter seed, wherein the programmable logic circuitry is reconfigurable to implement the circuit design using a second configuration image that is different than the first configuration image, and wherein placement of the second configuration image in the programmable logic circuitry is based on a second random fitter seed that is different than the first random fitter seed.   
     
     
         20 . The integrated circuit of  claim 19 , wherein:
 the first configuration image configures a first portion of the programmable logic circuitry as a quiet region and configures a second portion of the programmable logic circuitry as a toggling region; and   the second configuration image reconfigures the first portion of the programmable logic circuitry as the toggling region and reconfigures the second portion of the programmable logic circuitry as the quiet region.