Functionally redundant semiconductor dies and package

Abstract

Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

What is claimed: 
     
         1 . A semiconductor device, comprising:
 a first die, the first die including at least one metal trace;   the first die including at least first and second metal vias, wherein the first and second metal vias are conductively coupled to the metal trace;   the first die including first input/output (I/O) circuitry, wherein the first I/O circuitry is conductively coupled to the first metal via;   a second die on the first die, the second die including second I/O circuitry, wherein the second I/O circuitry is conductively coupled to the first metal via; and   a third die on the first die, the third die including third I/O circuitry, wherein the third I/O circuitry is conductively coupled to the second metal via.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first die has a first surface and a second surface opposite the first surface; wherein the metal trace extends substantially parallel to the first surface; and wherein the first and second metal vias extend substantially orthogonal to the first surface. 
     
     
         3 . The semiconductor device of  claim 1 , wherein at least one of the second or the third dies includes at least one IP core. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first die further comprises driver circuitry, wherein the driver circuitry conductively couples at least one of the first metal via or the second metal via to the metal trace. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising pads on the second surface of the first die. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising pads on the first surface of the first die, wherein the pads conductively couple the first die to at least one of the second die or the third die. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first die comprises a base die, and wherein at least one of the second die or the third die comprises a core die. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first metal via, the second metal via, and the metal trace comprise at least part of an electrical mesh network. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the first die further comprises driver circuitry. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the driver circuitry conductively couples either the first I/O circuitry, the second I/O circuitry, or the third I/O circuitry to an I/O interface contact. 
     
     
         11 . A semiconductor package, comprising:
 a substrate;   a first die on the substrate, the first die including at least one metal trace;   the first die including at least first and second metal vias, wherein the first and second metal vias are conductively coupled to the metal trace;   the first die including first input/output (I/O) circuitry, wherein the first I/O circuitry is conductively coupled to the first metal via;   a second die on the first die, the second die including second I/O circuitry, wherein the second I/O circuitry is conductively coupled to the first metal via; and   a third die on the first die, the third die including third I/O circuitry, wherein the third I/O circuitry is conductively coupled to the second metal via.   
     
     
         12 . The semiconductor package of  claim 11 , wherein the first die has a first surface and a second surface opposite the first surface; wherein the metal trace extends substantially parallel to the first surface; and wherein the first and second metal vias extend substantially orthogonal to the first surface. 
     
     
         13 . The semiconductor package of  claim 11 , wherein at least one of the second or the third dies includes at least one IP core. 
     
     
         14 . The semiconductor package of  claim 11 , wherein the first die further comprises driver circuitry, wherein the driver circuitry conductively couples at least one of the first metal via or the second metal via to the metal trace. 
     
     
         15 . The semiconductor package of  claim 11 , further comprising pads on the first surface of the first die, wherein the pads conductively couple the first die to at least one of the second die or the third die. 
     
     
         16 . The semiconductor package of  claim 11 , wherein the first die comprises a base die, and wherein at least one of the second die or the third die comprises a core die. 
     
     
         17 . The semiconductor package of  claim 11 , wherein the first metal via, the second metal via, and the metal trace comprise at least part of an electrical mesh network. 
     
     
         18 . The semiconductor package of  claim 11 , wherein the first die further comprises driver circuitry; and wherein the driver circuitry conductively couples either the first I/O circuitry, the second I/O circuitry, or the third I/O circuitry to an I/O interface contact. 
     
     
         19 . A system, comprising:
 a substrate;   a first die on the substrate, the first die including at least one metal trace;   the first die including at least first and second metal vias, wherein the first and second metal vias are conductively coupled to the metal trace;   the first die including first input/output (I/O) circuitry, wherein the first I/O circuitry is conductively coupled to the first metal via;   a second die on the first die, the second die including second I/O circuitry, wherein the second I/O circuitry is conductively coupled to the first metal via;   a third die on the first die, the third die including third I/O circuitry, wherein the third I/O circuitry is conductively coupled to the second metal via; and   a power source, wherein the power source is conductively coupled to the substrate.   
     
     
         20 . The system of  claim 19 , wherein the first die further comprises driver circuitry; and wherein the driver circuitry conductively couples either the first I/O circuitry, the second I/O circuitry, or the third I/O circuitry to an I/O interface contact.