Semiconductor package method of fabricating semiconductor package and method of fabricating re-distribution structure

Abstract

A semiconductor package may include a lower re-distribution layer, a stack bonded to a portion of the lower re-distribution layer, a semiconductor chip on a top surface of the lower re-distribution layer, and an upper re-distribution layer on the semiconductor chip and the stack.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 a lower re-distribution layer;   a stack provided on a first region of a top surface of the lower re-distribution layer;   a semiconductor chip provided on a second region of the top surface of the lower re-distribution layer; and   an upper re-distribution layer on the semiconductor chip and the stack,   wherein the upper re-distribution layer is electrically connected to the lower re-distribution layer via the stack.   
     
     
         2 . The semiconductor package of  claim 1 , wherein the lower re-distribution layer and the stack are electrically connected to each other via a connection ball. 
     
     
         3 . The semiconductor package of  claim 1 , wherein the stack comprises:
 a first insulating layer disposed on the top surface of the lower re-distribution layer;   a second insulating layer disposed on a top surface of the first insulating layer;   a first via penetrating the first insulating layer;   a second via penetrating the second insulating layer; and   a first interconnection line electrically connecting the first via to the second via.   
     
     
         4 . The semiconductor package of  claim 3 , wherein a vertically extending central axis of the second via is spaced apart from a vertically extending central axis of the first via. 
     
     
         5 . The semiconductor package of  claim 3 ,
 wherein the lower re-distribution layer comprises a lower redistribution insulator, and   wherein the lower redistribution insulator, the first insulating layer, and the second insulating layer comprise a photo imageable dielectric (PID) material.   
     
     
         6 . The semiconductor package of  claim 5 , further comprising:
 a mold layer provided to enclose an outer side surface of the stack and the semiconductor chip; and   an underfill layer interposed between the lower re-distribution layer and the stack,   wherein the mold layer comprises a material different from the PID material.   
     
     
         7 . The semiconductor package of  claim 3 , wherein the first insulating layer and the second insulating layer are provided to form a step structure in a side facing the semiconductor chip. 
     
     
         8 . The semiconductor package of  claim 3 , wherein the first via has an upwardly increasing width. 
     
     
         9 . The semiconductor package of  claim 2 , wherein the lower re-distribution layer and the semiconductor chip are electrically connected to each other via an intermediate ball. 
     
     
         10 . The semiconductor package of  claim 9 , further comprising:
 an underfill layer on the lower re-distribution layer,   wherein the underfill layer is disposed beneath the stack and the semiconductor chip.   
     
     
         11 . The semiconductor package of  claim 10 , wherein the underfill layer surrounds the connection ball and the intermediate ball. 
     
     
         12 . A semiconductor package, comprising:
 a lower re-distribution layer;   a stack on the lower re-distribution layer;   a semiconductor chip on the lower re-distribution layer; and   a connection ball between the lower re-distribution layer and the stack,   wherein the stack and the semiconductor chip are horizontally spaced apart from each other, and   wherein the stack comprises:
 a first insulating layer; 
 a second insulating layer on the first insulating layer; 
 a first via penetrating the first insulating layer; and 
 a second via penetrating the second insulating layer. 
   
     
     
         13 . The semiconductor package of  claim 12 , further comprising:
 an upper re-distribution layer on the semiconductor chip and the stack,   wherein the upper re-distribution layer is electrically connected to the lower re-distribution layer via the stack.   
     
     
         14 . The semiconductor package of  claim 12 , wherein a vertically extending central axis of the second via is spaced apart from a vertically extending central axis of the first via. 
     
     
         15 . The semiconductor package of  claim 12 , wherein the first insulating layer and the second insulating layer comprise a photo imageable dielectric (PID) material. 
     
     
         16 . The semiconductor package of  claim 12 , wherein the first via has an upwardly increasing width. 
     
     
         17 . The semiconductor package of  claim 12 , wherein the lower re-distribution layer and the semiconductor chip are electrically connected to each other via an intermediate ball. 
     
     
         18 . The semiconductor package of  claim 17 , further comprising:
 an underfill layer on the lower re-distribution layer; and   a mold layer provided to enclose a side surface of the semiconductor chip,   wherein an upper surface of the underfill layer contacts a bottom surface of the molding layer.   
     
     
         19 . The semiconductor package of  claim 12 , wherein the stack comprises:
 a third insulating layer on the second insulating layer; and   a third via penetrating the third insulating layer.   
     
     
         20 . The semiconductor package of  claim 19 , wherein the first insulating layer and the second insulating layer are provided to form a step structure in a side facing the semiconductor chip.