Systems and methods for scalable and coherent memory devices

Abstract

Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.

What is claimed is: 
     
         1 . A device for providing a storage resource, the device comprising:
 a first controller coupled to a network interface, wherein the first controller is operable with a cache coherent protocol;   a second controller coupled to the first controller and coupled to a first memory, the second controller performing at least one operation associated with a cache of the device; and   a second memory coupled to at least one of the first controller or the second controller.   
     
     
         2 . The device of  claim 1 , wherein the device:
 receives a configuration information from a host;   configures the device to operate the second controller as one of a software-based cache or a hardware based cache in a boot-time mode of operation;   receives, via the first controller, data via the network interface using the cache coherent protocol;   performs at least one second operation on the data to generate second data, and   stores the second data on the second memory based on the cache coherent protocol.   
     
     
         3 . The device of  claim 1 , wherein the cache coherent protocol comprises a compute express link (CXL) protocol and wherein the device further comprises a profiler that determines at least one capability associated with the device and provides the capability to a host. 
     
     
         4 . The device of  claim 1 , wherein the device further comprises a third controller coupled to a third memory, the third memory comprising a non-volatile memory. 
     
     
         5 . The device of  claim 1 , wherein the first memory comprises a first volatile memory and the second memory comprises a second volatile memory. 
     
     
         6 . The device of  claim 5 , wherein the first volatile memory comprises a double-data rate memory or a low-power double data-data rate memory. 
     
     
         7 . The device of  claim 1 , wherein the first memory comprises a first non-volatile memory and the second memory comprises a second non-volatile memory. 
     
     
         8 . The device of  claim 7 , wherein the first non-volatile memory comprises a three-dimensional flash memory. 
     
     
         9 . The device of  claim 1 , wherein the device comprises at least one of a M.2 form factor, an E1.L form factor, a E1.S form factor, a E3 S/L form factor, a U.2 form factor, an NF1 form factor, an full height, half length (FHHL) add-in card (AIC) form factor, or an half height, half length (HHHL) AIC form factor. 
     
     
         10 . The device of  claim 1 , wherein the second controller comprises at least one of a flow control module, a cache addressing module, or a cache policy module. 
     
     
         11 . The device of  claim 1 , wherein the second controller comprises at least one of a channel request queue, a volatile-memory request scheduler, or a volatile-memory command scheduler. 
     
     
         12 . The device of  claim 1 , wherein the device further comprises an accelerator or a network interface card (NIC). 
     
     
         13 . A system for providing a storage resource, the system comprising:
 a first controller coupled to a network interface, wherein the first controller is operable with a cache coherent protocol;   a second controller coupled to the first controller coupled to a first memory, the second controller performing at least one operation associated with a cache; and   a second memory coupled to at least one of the first controller or the second controller.   
     
     
         14 . The system of  claim 13 , wherein the system:
 receives, via the first controller, data via the network interface using the cache coherent protocol,   performs at least one second operation on the data to generate second data, and   stores the second data on the first memory or the second memory.   
     
     
         15 . The system of  claim 13 , wherein the cache coherent protocol comprises a CXL protocol and the first controller and the system further comprises a profiler that determines at least one capability associated with the system and provides the capability to a host. 
     
     
         16 . The system of  claim 13 , wherein the first memory comprises a volatile memory and the second memory comprises a volatile memory. 
     
     
         17 . The system of  claim 16 , wherein the volatile memory comprises a double-data rate memory or a low-power double data-data rate memory. 
     
     
         18 . The system or  claim 13 , wherein the first memory comprises a non-volatile memory and the second memory comprises a non-volatile memory. 
     
     
         19 . A method for providing a storage resource, the method comprising:
 operating a first controller coupled to a network interface in accordance with a cache coherent protocol;   performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and   storing the data on a second memory coupled to one of the first controller or the second controller.   
     
     
         20 . The method of  claim 19 , wherein the method further comprises:
 receiving a configuration information from a host;   operating the second controller as one of a software-based cache or a hardware based cache in a boot-time mode of operation;   receiving, via the first controller, second data via the network interface using the cache coherent protocol;   performing at least one second operation on the second data to generate third data, and   storing the second data on the second memory based on the cache coherent protocol.