US2021367097A1PendingUtilityA1
Mesa formation for wafer-to-wafer bonding
Est. expirySep 11, 2038(~12.1 yrs left)· nominal 20-yr term from priority
H10H 20/0364H10H 20/036H10H 20/0363H10H 20/034H10H 20/855H10H 20/819H10H 20/8162H10H 20/01H10H 29/142H10H 20/018G02B 27/0093H01L 33/20H01L 33/0095H01L 2933/0033
68
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
Disclosed herein are techniques for wafer-to-wafer bonding for manufacturing light emitting diodes (LEDs). In some embodiments, a method of manufacturing LEDs includes etching a semiconductor material to form a plurality of adjacent mesa shapes. The semiconductor material includes one or more epitaxial layers. The method also includes forming a passivation layer to fill gaps between the adjacent mesa shapes, planarizing the passivation layer to expose a contact layer formed on a first surface of the semiconductor material, and bonding a base wafer to the contact layer.
Claims
exact text as granted — not AI-modified1 . A method comprising:
etching a semiconductor material to form a plurality of adjacent mesa shapes, the semiconductor material comprising one or more epitaxial layers; forming a passivation layer that completely fills gaps between the adjacent mesa shapes; planarizing the passivation layer, wherein the planarizing exposes a contact layer formed on a first surface of the semiconductor material; and bonding a base wafer to the contact layer.
2 . The method of claim 1 , wherein the bonding of the base wafer is performed after the planarizing exposes the contact layer.
3 . The method of claim 1 , further comprising:
forming the contact layer, wherein the forming of the contact layer comprises depositing an electrically conductive material onto the first surface of the semiconductor material before etching the semiconductor material to form the plurality of adjacent mesa shapes.
4 . The method of claim 1 , wherein the planarizing of the passivation layer comprises polishing back the passivation layer to form a flat surface comprising the passivation layer.
5 . The method of claim 1 , wherein planarizing of the passivation layer comprises grinding or chemically etching the passivation layer to form a flat surface comprising the passivation layer.
6 . The method of claim 1 , further comprising, before bonding the base wafer to the contact layer:
depositing a bonding layer on the contact layer, wherein the base wafer is bonded to the contact layer via the bonding layer.
7 . The method of claim 6 , wherein the base wafer is bonded to the bonding layer by metal-to-metal bonding, eutectic bonding, or oxide bonding.
8 . The method of claim 6 , wherein the bonding layer and contact layer are made of a same material.
9 . The method of claim 1 , further comprising:
removing a substrate from a second surface of the semiconductor material, wherein the second surface of the semiconductor material is opposite to the first surface of the semiconductor material; and patterning a trench between each pair of the adjacent mesa shapes to form a plurality of light-emitting diodes after removing the substrate.
10 . The method of claim 9 , wherein the removing of the substrate is performed after bonding the base wafer to the contact layer.
11 . The method of claim 10 , wherein the patterning of the trench between each pair of the adjacent mesa shapes comprises etching through the semiconductor material, through the contact layer, through the bonding layer, and at least partially through the base wafer.
12 . The method of claim 10 , wherein the patterning of the trench between each pair of the adjacent mesa shapes comprises etching the passivation layer such that each trench extends through a gap that was filled by the passivation layer.
13 . The method of claim 9 , wherein the one or more epitaxial layers are grown on the substrate, and wherein the etching of the semiconductor material to form the plurality of adjacent mesa shapes is stopped before reaching the substrate.
14 . The method of claim 9 , wherein the base wafer comprises a plurality of driver circuits, and wherein the trenches are not vertically aligned with the plurality of driver circuits.
15 . The method of claim 9 , wherein the substrate is removed through applying a focused laser beam or through heating the substrate.
16 . The method of claim 9 , further comprising forming an optical element on the second surface of the semiconductor material to enhance a spontaneous emission rate of a first light-emitting diode among the plurality of light-emitting diodes, wherein the optical element is formed at a light exit surface of the first light-emitting diode.
17 . The method of claim 16 , wherein the optical element comprises a lens, a graded index element, or a diffraction grating.
18 . The method of claim 1 , wherein the base wafer comprises a plurality of driver circuits, and wherein the method further comprises aligning the plurality of driver circuits with the adjacent mesa shapes while bonding the base wafer to the contact layer.
19 . The method of claim 1 , wherein the etching of the semiconductor material to form the plurality of adjacent mesa shapes produces mesa shapes with non-parallel side walls.
20 . The method of claim 1 , further comprising, before forming the passivation layer, depositing a reflective layer on a side wall of each of the adjacent mesa shapes.Join the waitlist — get patent alerts
Track US2021367097A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.