Via rail solution for high power electromigration

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.

What is claimed is: 
     
         1 . An integrated chip, comprising:
 a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate;   a plurality of conductive contacts electrically coupled to the plurality of source/drain regions;   a first interconnect wire arranged over the plurality of conductive contacts;   a second interconnect wire arranged over the first interconnect wire;   a via rail contacting the first interconnect wire and the second interconnect wire, wherein the via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance; and   wherein the outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.   
     
     
         2 . The integrated chip of  claim 1 , wherein the plurality of gate structures continuously extend from directly between adjacent ones of the plurality of source/drain regions to directly below the via rail. 
     
     
         3 . The integrated chip of  claim 1 ,
 wherein the first interconnect wire comprises a first additional outer sidewall that faces the outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a second non-zero distance; and   wherein the second interconnect wire comprises a second additional outer sidewall that faces the outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a third non-zero distance.   
     
     
         4 . The integrated chip of  claim 1 ,
 wherein the plurality of gate structures respectively have a length extending in a first direction and a width extending in a second direction, the width less than the length; and   wherein the plurality of gate structures protrude outward from below the via rail in the first direction.   
     
     
         5 . The integrated chip of  claim 1 ,
 wherein two of the plurality of gate structures are arranged between closest neighboring ones of the plurality of conductive contacts along a first cross-sectional view; and   wherein the via rail continuously extends past outermost sidewalls of the closest neighboring ones of the plurality of conductive contacts along the first cross-sectional view.   
     
     
         6 . The integrated chip of  claim 1 , wherein the via rail is configured to enable current to flow along both a first direction that is perpendicular to an upper surface of the substrate and along a second direction that is parallel to the upper surface of the substrate. 
     
     
         7 . The integrated chip of  claim 1 , wherein the plurality of source/drain regions comprise epitaxial source/drain regions disposed on a fin of semiconductor material. 
     
     
         8 . The integrated chip of  claim 7 , wherein the via rail laterally extends past an outer sidewall of the fin of semiconductor material. 
     
     
         9 . An integrated chip, comprising:
 a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate;   a plurality of conductive contacts electrically coupled to the plurality of source/drain regions;   a first interconnect wire arranged over the plurality of conductive contacts;   a second interconnect wire arranged over the first interconnect wire;   a via rail contacting the first interconnect wire and the second interconnect wire, wherein the via rail continuously extends past the plurality of gate structures;   an inter-level dielectric (ILD) surrounding the via rail; and   a conductive via laterally separated from the via rail by the ILD, wherein the conductive via and the via rail have a substantially same width and different lengths.   
     
     
         10 . The integrated chip of  claim 9 , wherein the first interconnect wire continuously extends from a lower surface contacting the plurality of conductive contacts to an upper surface contacting the via rail. 
     
     
         11 . The integrated chip of  claim 9 , further comprising:
 an additional via contacting an upper surface of the second interconnect wire at a location that is directly above an upper surface of the via rail.   
     
     
         12 . The integrated chip of  claim 9 , wherein an upper surface of the first interconnect wire laterally extends past opposing sides of the via rail. 
     
     
         13 . The integrated chip of  claim 9 , further comprising:
 a plurality of middle-end-of-the-line (MEOL) structures continuously extending from directly over the plurality of source/drain regions to laterally outside the plurality of source/drain regions and directly below both the via rail and the first interconnect wire.   
     
     
         14 . The integrated chip of  claim 9 , wherein the first interconnect wire is a disposed on a closest interconnect wire layer to the substrate and the second interconnect wire is disposed on a second closest interconnect wire layer to the substrate. 
     
     
         15 . The integrated chip of  claim 9 , wherein the via rail and the conductive via are both on and in contact with an upper surface of the first interconnect wire. 
     
     
         16 . The integrated chip of  claim 9 ,
 wherein the conductive via is disposed directly over one of the plurality of source/drain regions; and   wherein the conductive via and the via rail have the different lengths as measured along a cross-sectional view that includes two or more of the plurality of gate structures.   
     
     
         17 . The integrated chip of  claim 9 , wherein the via rail has a first length that is more than five times a second length of the conductive via. 
     
     
         18 . An integrated chip, comprising:
 a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate;   a plurality of conductive contacts electrically coupled to the plurality of source/drain regions;   a first interconnect wire arranged over the plurality of conductive contacts;   a second interconnect wire arranged over the first interconnect wire;   a via rail contacting the first interconnect wire and the second interconnect wire, wherein the via rail continuously extends past the plurality of gate structures;   wherein the via rail has a first angled sidewall that is oriented at a first angle with respect to a line that is normal to an upper surface of the substrate; and   wherein the first interconnect wire has a second angled sidewall that is oriented at a second angle with respect to the line that is normal to the upper surface of the substrate, the first angle is different than the second angle.   
     
     
         19 . The integrated chip of  claim 18 , wherein the via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions, that is laterally separated from the plurality of source/drain regions by a non-zero distance, and that continuously extends past two or more of the plurality of gate structures. 
     
     
         20 . The integrated chip of  claim 18 , wherein the plurality of gate structures continuously extend from directly between adjacent ones of the plurality of source/drain regions to directly below the via rail.