US2021366709A1PendingUtilityA1

Semiconductor device and method for manufacturing the same

Assignee: SEMICONDUCTOR ENERGY LABPriority: Jun 30, 2009Filed: Jul 29, 2021Published: Nov 25, 2021
Est. expiryJun 30, 2029(~2.9 yrs left)· nominal 20-yr term from priority
H10P 14/3434H10P 14/38H10D 30/6717H10D 30/6758H10D 30/6755H10D 86/423H10D 86/60H10D 99/00H10D 30/6757H10D 30/6756H10D 30/6713H10D 30/0321H10D 30/0316H01L 21/02565H01L 29/66765H01L 29/78618H01L 29/7869H01L 21/02664H01L 29/78696H01L 27/1225H01L 29/66969H01L 29/78693
78
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (which is for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. Besides impurities such as moisture existing in the oxide semiconductor film, heat treatment causes reduction of impurities such as moisture existing in the gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor film and are in contact with the oxide semiconductor film.

Claims

exact text as granted — not AI-modified
1 . (canceled) 
     
     
         2 . A method for manufacturing a semiconductor device comprising the steps of:
 forming an oxide semiconductor layer;   preforming a first heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer;   forming a source electrode overlapping with a first region of the oxide semiconductor layer and a drain electrode overlapping with a second region of the oxide semiconductor layer;   forming an oxide insulating layer in contact with a third region of the oxide semiconductor layer;   diffusing oxygen from the oxide insulating layer to the third region of the oxide semiconductor layer, thereby increasing resistance of the third region than resistance of the first and second regions; and   performing a second heat treatment after forming the oxide insulating layer in contact with the third region of the oxide semiconductor layer.   
     
     
         3 . The method according to  claim 2 , wherein the third region is located between the first region and the second region in the oxide semiconductor layer and comprises a channel formation region. 
     
     
         4 . The method according to  claim 2 , wherein the first heat treatment is performed at a first temperature and the second heat treatment is performed at a second temperature lower than the first temperature. 
     
     
         5 . The method according to  claim 4 , wherein the first temperature is equal to or higher than 400° C. and the second temperature is equal to or higher than 150° C. and lower than 350° C. 
     
     
         6 . The method according to  claim 2 , wherein the first heat treatment is performed under one of a nitrogen atmosphere and a rare gas atmosphere. 
     
     
         7 . The method according to  claim 2 , wherein the second heat treatment is performed under one of a nitrogen atmosphere and an air atmosphere. 
     
     
         8 . The method according to  claim 2 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 
     
     
         9 . The method according to  claim 2 ,
 wherein by performing the first heat treatment, a carrier concentration in the oxide semiconductor layer is increased, and   wherein by performing the second heat treatment, the carrier concentration in the oxide semiconductor layer is reduced.   
     
     
         10 . A method for manufacturing a semiconductor device comprising the steps of:
 forming an oxide semiconductor layer;   forming an n-type oxide semiconductor layer by preforming a first heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer;   forming a source electrode overlapping with a first region of the n-type oxide semiconductor layer and a drain electrode overlapping with a second region of the n-type oxide semiconductor layer;   forming an oxide insulating layer in contact with a third region of the n-type oxide semiconductor layer;   forming an i-type oxide semiconductor layer by diffusing oxygen from the oxide insulating layer to the third region of the n-type oxide semiconductor layer; and   performing a second heat treatment after forming the oxide insulating layer.   
     
     
         11 . The method according to  claim 10 , wherein the third region is located between the first region and the second region in the oxide semiconductor layer and comprises a channel formation region. 
     
     
         12 . The method according to  claim 10 , wherein the first heat treatment is performed at a first temperature and the second heat treatment is performed at a second temperature lower than the first temperature. 
     
     
         13 . The method according to  claim 12 , wherein the first temperature is equal to or higher than 400° C. and the second temperature is equal to or higher than 150° C. and lower than 350° C. 
     
     
         14 . The method according to  claim 10 , wherein the first heat treatment is performed under one of a nitrogen atmosphere and a rare gas atmosphere. 
     
     
         15 . The method according to  claim 10 , wherein the second heat treatment is performed under one of a nitrogen atmosphere and an air atmosphere. 
     
     
         16 . The method according to  claim 10 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc. 
     
     
         17 . The method according to  claim 10 ,
 wherein by performing the first heat treatment, a carrier concentration in the oxide semiconductor layer is increased, and   wherein by performing the second heat treatment, the carrier concentration in the oxide semiconductor layer is reduced.

Join the waitlist — get patent alerts

Track US2021366709A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.