Microprocessor architecture having alternative memory access paths

Abstract

The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.

What is claimed is: 
     
         1 . A method comprising:
 fetching, by at least one processor, at least one instruction of a first instruction set from a cache memory for execution by the at least one processor, wherein the at least one instruction of the first instruction set is loaded to the cache memory in a fixed-size data block fetched from main memory via a block oriented cache-access path that provides fixed-size data block access to the main memory; and   offloading, by the at least one processor, at least one instruction of a second instruction set for execution by at least one heterogeneous functional unit, wherein the at least one instruction of the second instruction set is fetched directly from the main memory to the at least one heterogeneous functional unit via an address oriented cache-bypass path that provides individually-addressed data access to the main memory.   
     
     
         2 . The method of  claim 1 , wherein the at least one processor is configured to execute instructions of the first instruction set, and the at least one heterogeneous functional unit is configured to execute instructions of the second instruction set that is different from the first instruction set. 
     
     
         3 . The method of  claim 1 , wherein fetching the at least one instruction of the first instruction set from the cache memory for execution by the at least one processor includes:
 determining whether the at least one instruction is present in cache memory;   fetching the fixed-size data block including the at least one instruction of the first instruction set from the main memory to the cache memory via the block oriented cache-access path that provides fixed-size data block access to the main memory; and   loading the at least one instruction of the first instruction set from the cache memory to the at least one processor.   
     
     
         4 . The method of  claim 1 , wherein the fixed-size data block loaded to the cache memory from the main memory includes instructions in addition to the at least one instruction of the first instruction set, and wherein the at least one instruction of the second instruction set is fetched directly from the main memory to the at least one heterogeneous functional unit is fetched individually without other instructions. 
     
     
         5 . The method of  claim 1 , further comprising determining whether an instruction to be executed is an instruction of the first instruction set or an instruction of the second instruction set. 
     
     
         6 . The method of  claim 5 , further comprising:
 fetching the at least one instruction of the first instruction set from the cache memory for execution by the at least one processor in response to determining that the instruction to be executed is an instruction of the first instruction set; and   offloading the at least one instruction of the second instruction set for execution by at least one heterogeneous functional unit in response to determining that the instruction to be executed is an instruction of the second instruction set.   
     
     
         7 . The method of  claim 1 , wherein the main memory comprises scatter/gather memory configured for individually-addressed data access, and is configured to emulate block data access for fetching the fixed-size data block fetched from the main memory to the cache memory via the block oriented cache-access path. 
     
     
         8 . A system comprising:
 at least one processor configured to fetch at least one instruction of a first instruction set for execution by the at least one processor from a main memory via a block oriented cache-access path, wherein the block oriented cache-access path is configured to provide fixed-size data block access to the main memory; and   at least one heterogeneous functional unit configured to fetch at least one instruction of a second instruction set from the main memory via an address oriented cache-bypass path, wherein the address oriented cache-bypass path provides individually-addressed data access to the main memory, and wherein the at least one instruction of the first instruction set is offloaded from the at least one processor to the at least one heterogeneous functional unit for execution by the at least one heterogeneous functional unit.   
     
     
         9 . The system of  claim 8 , wherein the at least one processor is configured to execute instructions of the first instruction set, and the at least one heterogeneous functional unit is configured to execute instructions of the second instruction set that is different from the first instruction set. 
     
     
         10 . The system of  claim 8 , wherein the block oriented cache-access path couples the main memory to a cache memory, and wherein the configuration of the at least one processor to fetch the at least one instruction of the first instruction set via the block oriented cache-access path includes configuration of the at least one processor to:
 cause at least one fixed-size data block to be fetched from the main memory and to be loaded to the cache memory when the at least one instruction of the first instruction set is absent from the cache memory, the at least one fixed-size data block including at least one instruction of the first instruction set; and   fetch the at least one instruction of the first instruction set from the cache memory.   
     
     
         11 . The system of  claim 8 , wherein the fixed-size data block access to the main memory returns data in addition to data referenced by a cache memory access by the at least one processor, and wherein the individually-addressed data access returns only data referenced by a physical address access by the at least one heterogeneous functional unit. 
     
     
         12 . The system of  claim 8 , wherein the at least one processor is further configured to determine whether an instruction to be executed is an instruction of the first instruction set or an instruction of the second instruction set. 
     
     
         13 . The system of  claim 12 , wherein the at least one processor is further configured to:
 fetch the at least one instruction of the first instruction set from a cache memory for execution by the at least one processor in response to a determination that the instruction to be executed is an instruction of the first instruction set; and   offloading the at least one instruction of the second instruction set for execution by at least one heterogeneous functional unit in response to determining that the instruction to be executed is an instruction of the second instruction set.   
     
     
         14 . The system of  claim 8 , wherein the main memory comprises scatter/gather memory configured for individually-addressed data access, and is configured to emulate block data access for fetching a fixed-size data block from the main memory via the block oriented cache-access path. 
     
     
         15 . The system of  claim 8 , further comprising:
 a cache interrogation path coupling a cache memory to the at least one heterogeneous functional unit, wherein the cache interrogation path is configured to provide information regarding encached data to the at least one heterogeneous functional unit in response to an interrogation by the at least one heterogeneous functional unit regarding referenced data to be accessed by the at least one heterogeneous functional unit, the referenced data including the at least one instruction of the second instruction set.   
     
     
         16 . The system of  claim 15 , wherein the cache interrogation path is configured to initiate loading a fixed-size cache block containing the referenced data to the main memory for individually-addressed data access of the referenced data from the main memory by the at least one heterogeneous functional unit using the address oriented cache-bypass path. 
     
     
         17 . The system of  claim 15 , wherein the cache interrogation path is configured to invalidate the referenced data in the cache memory in association with individually-addressed data access of the referenced data from the main memory by the at least one heterogeneous functional unit using the address oriented cache-bypass path. 
     
     
         18 . A method comprising:
 accessing, by at least one processor, a first portion of data from a main memory via a block oriented cache-access path, wherein the block oriented cache-access path is configured to provide fixed-size data block access to the main memory; and   accessing, by at least one heterogeneous functional unit, a second portion of data from the main memory via an address oriented cache-bypass path, wherein the address oriented cache-bypass path provides individually-addressed data access to the main memory, and wherein the second portion of data includes at least one instruction offloaded from the at least one processor to the at least one heterogeneous functional unit for execution by the at least one heterogeneous functional unit.   
     
     
         19 . The method of  claim 18 , wherein accessing the first portion of data from the main memory via the block oriented cache-access path includes:
 determining whether the first portion of data is present in cache memory;   fetching a fixed-size data block including the first portion of data from the main memory to the cache memory via the block oriented cache-access path; and   loading the first portion of data from the cache memory to the at least one processor.   
     
     
         20 . The method of  claim 18 , wherein accessing the second portion of data from the main memory via the address oriented cache-bypass path includes:
 offloading, by the at least one processor, execution of the at least one instruction included in the second portion of data to the at least one heterogeneous functional unit; and   fetching the at least one instruction directly from the main memory to the at least one heterogeneous functional unit via the address oriented cache-bypass path by referencing an individual address of the at least one instruction in the main memory to individually-addressed data access the address of the at least one instruction.